Method for forming floating gates within NVM process

Details Method for forming floating gates within NVM process Method for forming floating gates within NVM process

2005-08-22

2008-10-14

Le, Thao P. (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257SE21680

Reexamination Certificate

active

07435646

ABSTRACT:
A semiconductor process and apparatus includes forming a semiconductor device by depositing a layer of nitride (20) over a semiconductor structure (10), patterning and etching the nitride layer to form a patterned nitride layer (42, 44), depositing a layer of polysilicon (62), planarizing the polysilicon layer with a CMP process to remove any portion of the polysilicon layer (62) above the patterned dielectric layer (42, 44), and then removing the patterned nitride layer (42, 44), thereby defining one or more polysilicon features (72, 74, 76) that can be used as floating gates, transistors gates, bit lines or any other semiconductor device feature.

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patent: 2004/0152266 (2004-08-01), Chuang et al.
patent: 2005/0170579 (2005-08-01), Hsu et al.

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