Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-11-17
2003-02-11
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S258000, C438S266000, C438S585000, C438S592000, C438S586000
Reexamination Certificate
active
06518125
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a method for forming a semiconductor devices process, and more particularly to a method for a capacitor having swing-like structure.
2. Description of the Prior Art
Recent, developments have included various techniques for increasing the density of integration of the semiconductor memory device and decreasing the voltage thereof. A control gate and a floating gate have long been utilized for forming a flash memory. Electrons are moved onto or removed from the floating gate of a given memory cell in order to program or erase its state. The floating gate is surrounded by an electrically insulated dielectric. Since the floating gate is well insulated, this type of memory device is not volatile; that is, the floating gate retains its charge for an indefinite period without any power being applied to the device. Moreover, if enough electrons are so injected into the floating gate, the conductivity of the channel of the field effect transistor of which the floating gate is a part is changed. Hence, a control gate is coupled with the floating gate through a dielectric layer and acts as a word line to enable reading or writing of a single selected cell in a two-dimensional array of cells.
One type of memory array integrated circuit chip includes elongated, spaced apart source and drain regions formed in a surface of a semiconductor substrate, wherein the source and drain regions form the bit lines of the memory. A two-dimensional array of floating gates has each floating gate positioned in a channel region between adjacent source and drain regions, while the control gate is positioned over each row of floating gates in a direction transverse to the source and drain regions, wherein the control gates are the word lines of the memory array.
The coupling ratio proceeds from writing and reading in the flash memory via electrons that are transmitted between floating gate and source/drain, wherein the coupling ratio is a rate that show real voltage transmitted from external voltage into the floating gate. Hence, the used voltage is as high as the coupling ratio, that is, the lose voltage is becoming more and more lower. On the other hand, if the coupling ratio is high, the requirements of operating voltage for programming or erasing will be lower, that is, the memory efficiency is great, and results in the flash memory can erase rapidly and efficiently. As shown in
FIG. 1A
, a conventional flash memory
100
has a floating gate
110
and a control gate
120
. Electrons flow through tunnel oxide layer
140
from drain
130
into floating gate
110
by tunnel effect or hot-channel, so as to arise threshold voltage of the flash memory
100
and to save data. Furthermore, electrons flow through tunnel oxide layer
140
from floating gate
110
into source
150
by tunnel effect or hot-channel, so as to decrease threshold voltage of the flash memory
100
and to erase data.
The circuit equivalent of flash memory
100
of above is shown in
FIG. 1B
, wherein the capacitance between floating gate
110
and control gate
120
is C
1
; the capacitance between floating gate
110
and source
150
is C
2
; the capacitance between floating gate
110
and channel
160
is C
3
and the capacitance between floating gate
110
and drain
130
is C
4
. Hence, the coupling ratio of the flash memory is defined that CR=C
1
/(C
1
+C
2
+C
3
+C
4
). Accordingly, capacitance C
1
between the floating gate
110
and control gate
120
has to be increased or C
2
, C
3
and C
4
to be decreased for raising the coupling ratio CR. The coupling ratio(CR) is also increased by increasing area of the dielectric layer between the floating gate
110
and control gate
120
or by decreasing tunnel region, due to the ratio of capacitance to surface area of dielectric layer or coupling area is direct proportion, and that the ratio of capacitance to distance is inverse proportion. However, coupling area is becoming more and more small when the dimension of device is shrink gradually, so that coupling ratio is decreased. Moreover, to be suitable for using low voltage, conventional process can only use the method for changing surface area to solve issue of coupling ratio.
A method for forming flash memory with the triple-poly according to the prior art is illustrated in
FIGS. 2A
to
2
C, wherein
FIG. 2A
is a plan view of flash memory array formed by FIG.
2
B and
FIG. 2C
, but shows only its major components for ease of understanding. First of all, a semiconductor substrate
200
has a tunnel oxide layer
212
thereon and poly regions
210
are located on the tunnel oxide layer
212
. Then, the souse/drain regions
220
are formed in the semiconductor substrate
200
by ion-implant. Next, the dielectric layers
230
are formed between the poly regions
210
. For increasing the coupling ratio of the flash memory, the poly regions
210
have crown surfaces
240
, so as to increase surfaces area of the gates. Dielectric layers are then formed along crown surfaces
240
of poly gates
210
by conforming method, wherein the batter material of the dielectric layer
250
is oxide-nitride-oxide layer (ONO). Afterward a polysilicon layer
260
is formed on the structure of above, as shown in FIG.
2
D.
FIG. 2D
is a plan view of flash memory array finished, but shows only its major components for ease of understanding, and the cross-sectional views of
FIG. 2C
takes along line III-III′ in FIG.
2
D.
Furthermore, conventional method for increasing the coupling ratio introduces to increase the surface area of gate. The common method for increasing the effective surface area of gate is used to arise three-dimensional structure. As shown in
FIG. 2B
, the crown surfaces
240
of the poly regions
210
have a height difference &Dgr;H. If the height difference &Dgr;H of the vertical structure of the sidewall is overhigh, it will make issue, which in the follow-up etched process of flash memory, that is, the semiconductor substrate will be damaged by means of overetching the dielectric layer or the oxide-nitride-oxide layer (ONO), so that the process window is difficult to control.
As shown in
FIGS. 2E
to
2
G, and the cross-sectional views of
FIG. 2E
to
2
G take along line II-II′ in FIG.
2
D. For finishing the circuit of flash memory, some regions have to proceed with follow-up etching process, such as the part of line II-II′ in
FIG. 2D
, so as to remove the poly regions
210
and the dielectric layers
250
within line II-II′ in
FIG. 2D
, as shown in FIG.
2
E. Although the selectivity between the poly region and the dielectric layer is good, the selectivity between the dielectric layer and the oxide-nitride-oxide layer (ONO) is bad. Hence, the dielectric layers
230
will be removed during the oxide-nitride-oxide layers(ONO)are etched, and it will damage source/drain regions
220
during the poly regions
210
are etched.
In accordance with the above description, a new and improved method for increasing coupling ratio of flash memory is therefore necessary, so as to raise the yield and quality of the follow-up process.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method is provided for fabricating the flash memory having high coupling ratio that substantially overcomes drawbacks of above mentioned problems arised from the conventional methods.
Accordingly, it is a main object of the present invention to provide a method for fabricating the flash memory having high coupling ratio. This invention can form the gate with large surface area, so as to increase the coupling ratio of flash memory. Hence, the present invention is appropriate for deep sub-micron technology to provide the semiconductor devices.
Another object of the present invention is to provide a method for forming the gate of flash memory. The present invention can increase the surface area of the gate by changing the surface profile of the substrate, wherein the surface shape is a swing-like shape. Fur
Everhart Caridad
Luu Chuong Anh
Macronix International Co. Ltd.
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