Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
2007-07-31
2007-07-31
Deo, Duy-Vu N. (Department: 1765)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S710000, C438S714000, C438S718000, C438S720000
Reexamination Certificate
active
10610498
ABSTRACT:
A ferroelectric memory capacitor is formed by forming a barrier layer, a first metal layer, a ferroelectric layer, a second metal layer, and a hard mask layer, on dielectric layer (70). Using the patterned hard mask layer (255), the layers are etched to form an etched barrier layer (205), and etched first metal layer (215), and etched ferroelectric layer (225), and etched second metal layers (235, 245). The etched layers form a ferroelectric memory capacitor (270) with sidewalls that form an angle with the plane of the upper surface of the dielectric layer (70) between 78° and 88°. The processes used to etch the layers are plasma processes performed at temperatures between 200° C. and 500° C.
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Celii Francis G.
Summerfelt Scott R.
Thakre Mahesh J.
Brady III W. James
Deo Duy-Vu N.
McLarty Peter K.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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