Method for forming dual gate in DRAM embedded with a logic...

Details Method for forming dual gate in DRAM embedded with a logic... Method for forming dual gate in DRAM embedded with a logic...

1999-11-03

2002-12-03

Meier, Stephen D. (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S530000, C438S587000, C438S592000

Reexamination Certificate

active

06489210

ABSTRACT:

This application claims priority to Korean Patent Application No. 570/1999, filed on Jan. 12, 1999, which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a method for forming a dual gate of a semiconductor device, which simplifies process steps and improves reliability of the semiconductor device.
2. Background of the Related Art
Generally, in fabrication of MOS devices, a single poly gate structure requires a buried PMOS transistor, which increases a short channel effect. In this case, it is difficult to fabricate a device having a gate length of 0.25 &mgr;m or less. A dual gate structure has been proposed, in which a P-poly gate is used in a PMOS transistor and an N-poly gate is used in an NMOS transistor.
FIGS. 1A
to
1
F show cross-sectional views iliustrating a related art method for forming a dual gate of a semiconductor device.
As shown in
FIG. 1A
, an isolation region
12
is partially formed in a semiconductor substrate
11
by a local oxidation of silicon (LOCOS) process or a trench isolation process. Thereafter, a P well region
13
and an N well region
14
are selectively formed in the semiconductor substrate
11
by impurity ion implantation.
The N well region
14
is masked during the formation of the P well region
13
, while the P well region
13
is masked during formation of the N well region
14
. (These steps are not illustrated in the figures).
As shown in
FIG. 1B
, a gate insulating film
15
is formed on the semiconductor substrate
11
. Subsequently, an undoped polysilicon layer
16
is deposited on the gate insulating film
15
. A first photoresist
17
is then selectively deposited on the polysilicon layer
16
. The first photoresist
17
is then patterned by exposure and developing processes to mask the polysilicon layer
16
of the N well region
14
. N-type impurity ions are then implanted into the exposed polysilicon layer
16
of the P well region
13
.
As shown in
FIG. 1C
, the first photoresist
17
is removed and then a second photoresist
17
a
is deposited on an entire surface of the semiconductor substrate including the polysilicon layer
16
, into which the N-type impurity ions were implanted. The second photoresist
17
a
is patterned by an exposure and developing processes to mask the polysilicon layer
16
(into which the N-type impurity ions are implanted) of the P well region
13
. P-type impurity ions are implanted into the exposed polysilicon layer
16
. The P-type the impurity ion implantation may also be performed prior to the N-type impurity ion implantation.
As shown in
FIG. 1D
, the second photoresist
17
a
is removed, and a tungsten silicide (WSi
2
) or a tungsten (W) layer
18
is formed on the polysilicon layer
16
. Subsequently, a third photoresist is deposited on the tungsten suicide layer
18
. The third photoresist is patterned by exposure and developing processes to form a photoresist pattern
19
. As shown in
FIG. 1D
, the photoresist pattern
19
is formed on the tungsten silicide layer
18
.
As shown in
FIG. 1E
, the tungsten silicide layer
18
, the polysilicon layer
16
, and the gate insulating film
15
are selectively removed by an etching process using the photoresist pattern
19
as a mask, to form a first gate electrode
20
and a second gate electrode
20
a.
The first gate electrode
20
is for an NMOS transistor and the second gate electrode
20
a
is for a PMOS transistor.
As shown in
FIG. 1F
, an oxide film or a nitride film is deposited on the entire surface of the semiconductor substrate including the gate electrodes
20
and
20
a,
and then etched back to form sidewall spacers
21
at both sides of the gate electrodes
20
and
20
a.
Thereafter, the N well region
14
is masked, and then impurity ions are implanted into the P well region
13
at both sides of the first gate electrode
20
to form first source/drain impurity ion diffused regions
22
.
Subsequently, the P well region
13
is masked, and then impurity ions are implanted into the N well region
14
at both sides of the second gate electrode
20
a
to form second source/drain impurity ion diffused regions
22
a.
The second source/drain impurity ion diffused region
22
a
may also be formed Prior to the first source/drain impurity ion diffused region
22
.
The related art method for forming a dual gate of a semiconductor device has several problems.
First, ion implantation is performed twice in order to dope impurity ions into the undoped polysilicon layer
16
. Also, ion implantation is performed twice when forming source/drain impurity ion diffused regions
22
,
22
a
corresponding to each of the transistors. This complicates process steps and increases the number of masks, thereby increasing cost.
Second, during ion implantation into the polysilicon layer
16
, the impurity ions pass through the polysilicon layer
16
if the polysilicon layer
16
is thin. This damages the gate insulating film
15
, thereby deteriorating its insulating characteristics.
Moreover, during boron ion implantation when forming a gate electrode for the PMOS transistor, the boron ions act to vary the threshold voltage of the device because its fast diffusion speed affects a channel region of the FET.
Third, since the tungsten silicide layer
18
formed on the polysilicon layer
16
has resistivity of about 100 &mgr;&OHgr;cm, it is impossible to reduce sheet resistance to 10 &OHgr;/sq or less, even though the polysilicon layer
16
is deposited to a thickness at 1000 Å or more.
Fourth, if a tungsten layer having resistivity lower than that of the tungsten silicide layer
18
is deposited on the polysilicon layer
16
to reduce resistance, titanium nitride (TiN) film or WN (tungsten nitride) film must additionally be formed to avoid reaction with silicon. This complicates process steps.
Fifth, a reoxidation process is required to restore damage caused to the gate insulating film
15
during the etching process for the formation of the gate electrode. However, selective reoxidation is required because the tungsten is likely to react with ambient O
2
. Therefore, selective oxidation should exactly satisfy possible oxidation conditions, such as a ratio of H
2
/O
2
, and oxidation temperature. In this case, there is a problem in that redundancy of the selective oxidation is low.
Finally, if a cell region and a logic region are formed in a single chip, the logic region requires a salicide process so that the logic region has a gate electrode material different from that of the cell region.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a method for forming a dual gate of a semiconductor device that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a method for forming a dual gate of a semiconductor device, which improves reliability of the device and simplifies process steps by forming the same gate electrode material in both a cell region and a logic region.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, in accordance with a first aspect of the present invention there is provided a method for forming a dual gate of a semiconductor device including the steps of sequentially stacking a gate insulating film, a semiconductor layer, and a low resistance metal layer on a semiconductor substrate having a first well of a first conductivity type and a second well of a second conductivity type, forming first and se

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