Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2008-04-08
2008-04-08
Estrada, Michelle (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S640000, C438S673000, C438S713000, C438S978000, C257SE21579
Reexamination Certificate
active
07354856
ABSTRACT:
The manufacture of damascene structures having improved performance, particularly, but not by way of limitation, dual damascene structures is provided. In one embodiment, a substrate having a conductive layer is formed in a first insulating layer. A protective layer is formed above the conductive layer. An etching stop layer is formed above the protective layer and the first insulating layer. A second insulating layer is formed above the etching stop layer. A first patterned photoresist layer is formed above the second insulating layer, the first patterned photoresist layer having a first pattern. The first pattern is etched into the second insulating layer and the etching stop layer to form a first opening. A via plug is filled at least partially in the first opening. An anti-reflective coating (ARC) layer is formed above the second insulating layer. A second patterned photoresist layer is formed above the ARC layer, the second photoresist layer having a second pattern. The second pattern is etched into portions of the via plug, second insulation layer, and the ARC layer to form a second opening, wherein a substantially tapered sidewall portion is formed at the interface of the first and second openings.
REFERENCES:
patent: 6251774 (2001-06-01), Harada et al.
patent: 6933240 (2005-08-01), Lazar et al.
patent: 2002-280450 (2002-09-01), None
Shue Shau-Lin
Tsai Ming-Hsing
Yeh Ming-Shih
Yu Chen-Hua
Birch & Stewart Kolasch & Birch, LLP
Estrada Michelle
Taiwan Semiconductor Manufacturing Co. Ltd.
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