Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1999-02-08
2000-06-13
Tsai, Jey
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438637, 438666, H01L 218242
Patent
active
060749121
ABSTRACT:
A method for forming different area vias of dynamic random access memory is disclosed. Essential points of the invention comprise spacer is only formed on gate of periphery circuit, and depth of passivation layer of periphery circuit gates is larger than depth of layer that capped over gates of cell. The provided method comprises following steps: First, capping a layer over gate of cell and gate of periphery circuit and then forming spacer on gate of periphery circuit, where depth of capping layer is smaller than depth of passivation layer of periphery circuit gate. Second, both gate of cell and gate of periphery circuit are cover by a dielectric layer. Third, vias in both cell and periphery circuit are formed simultaneously by photolithography and etching, where etching comprises etching of dielectric layer and etching of passivation layer. Advantageous of the invention is only a photolithography process is necessary and then throughput is enhanced.
REFERENCES:
patent: 5907779 (1999-05-01), Choi
patent: 6010953 (1999-05-01), Prall
Lin Kuen-Yow
Lin Kuo-Chi
Tsai Jey
United Microelectronics Corp.
LandOfFree
Method for forming different area vias of dynamic random access does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for forming different area vias of dynamic random access , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming different area vias of dynamic random access will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2067951