Method for forming devices with multiple spacer widths

Details Method for forming devices with multiple spacer widths Method for forming devices with multiple spacer widths

Filed on

2006-06-06

Date issued

2006-06-06

Examiner

Dickey, Thomas L. (Department: 2826)

Patent Class

Active solid-state devices (e.g., transistors, solid-state diode

SubClass

Field effect device

SubSubClass

Having insulated electrode

Other Related Categories

C438S230000, C438S241000, C257S408000

Type

Reexamination Certificate

Status

active

Patent number

07057237

Description

ABSTRACT:
A method is described for forming three or more spacer widths in transistor regions on a substrate. In one embodiment, different silicon nitride thicknesses are formed above gate electrodes followed by nitride etching to form spacers. Optionally, different gate electrode thicknesses may be fabricated and a conformal oxide layer is deposited which is subsequently etched to form different oxide spacer widths. A third embodiment involves a combination of different gate electrode thickness and different nitride thicknesses. A fourth embodiment involves selectively thinning an oxide layer over certain gate electrodes before etching to form spacers. Therefore, spacer widths can be independently optimized for different transistor regions on a substrate to enable better drive current in transistors with narrow spacers and improved SCE control in neighboring transistors with wider spacers. Better drive current is also obtained in transistors with shorter polysilicon thickness.

REFERENCES:
patent: 5021354 (1991-06-01), Pfiester
patent: 5874330 (1999-02-01), Ahn
patent: 6214715 (2001-04-01), Huang et al.
patent: 6248623 (2001-06-01), Chien et al.
patent: 6316304 (2001-11-01), Pradeep et al.
patent: 6344398 (2002-02-01), Hsu
patent: 6504192 (2003-01-01), Hasunuma

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