Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2006-04-18
2006-04-18
Norton, Nadine G. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S627000, C438S636000, C438S702000, C438S719000, C438S723000, C438S724000, C438S781000, C216S019000
Reexamination Certificate
active
07030031
ABSTRACT:
This invention relates to the manufacture of dual damascene interconnect structures in integrated circuit devices. Specifically, a method is disclosed for forming a single or dual damascene structure in a low-k dielectric thin film utilizing a planarizing material and a diffusion barrier material. In a preferred dual damascene embodiment of this method, the vias are formed first in the dielectric material, then the planarizing material is deposited in the vias and on the dielectric material, and the barrier material is deposited on the planarizing material. The trenches are then formed lithographically in the imaging material, etched through the barrier material into the planarizing material, and the trench pattern is transferred to the dielectric material. During and following the course of these etch steps, the imaging, barrier and planarizing materials are removed. The resultant dual damascene structure may then be metallized. With this method, the problem of photoresist poisoning by the interlevel dielectric material is alleviated.
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Biolsi Peter E.
Cote William J.
Edelstein Daniel C.
Fritche John
Upham Allan W.
Chen Eric B.
International Business Machines - Corporation
Jaklitsch Lisa U.
Norton Nadine G.
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