Method for forming cylindrical DRAM capacitors

Details Method for forming cylindrical DRAM capacitors Method for forming cylindrical DRAM capacitors

1997-05-06

2001-07-10

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S396000

Reexamination Certificate

active

06258662

ABSTRACT:

FIELD OF THE INVENTION
The present invention generally relates to a method for forming cylindrical dynamic random access memory (DRAM) capacitors and more particularly, relates to a method for forming stacked capacitors in DRAM devices by first forming a polysilicon plug for contacting the wafer and then forming crown-shaped upper and lower electrodes on the polysilicon plug. The method is compatible with the chemical mechanical polishing technique and can be used to form stacked capacitors in the less than 0.18 micron technology.
BACKGROUND OF THE INVENTION
DRAM cells have been widely used in modern semiconductor devices. They have been named as dynamic because the cells can retain information only for a limited time and they must be read and refreshed periodically. This is in contrast to a static random access memory cell which does not require periodic refresh signals in order to retain stored data. In a typical DRAM cell, the structure includes a transistor and a storage capacitor. When DRAM cells were first developed, planar type storage capacitors which occupy large wafer surface areas are used. As the circuit density increases in modern semiconductor devices where smaller chips are being made and are being packed with an ever-increasing number of circuits, the specific capacitance of a storage capacitor must be increased in order to meet such demands.
Different approaches have been used in achieving higher capacitance on limited real usage of wafer real estate. For instance, one solution is to store charges vertically in a trench which requires a deep trench formation and encounters significant processing difficulties. The second solution is to build a stacked capacitor on top of the transistor which allows a smaller cell to be built without losing storage capacity. The solution of using a stacked capacitor has become a more accepted and popular approach in the semiconductor fabrication industries.
In modern DRAM cells, small dimension and high capacitance value per unit area are therefore desirable characteristics for achieving high charge storage capacity. A DRAM capacitor is normally formed by at least two layers of electrically conductive material and one layer of a dielectric material. For example, a widely used DRAM capacitor utilizes a thin oxide layer sandwiched between two polysilicon layers to produce a high capacitance capacitor cell. The capacitor can be built by stacking over the bit line on the surface of a silicon substrate. The effective capacitance of a stacked cell is increased over that of a conventional planar cell due to its increased surface area.
A typical 16-Mb DRAM cell
10
having a stacked capacitor
20
built on top is shown in FIG.
1
. The DRAM cell
10
can be formed in the following manner. First, standard CMOS fabrication steps are used to form the transistor all the way through the gate oxide growth process. To form the word lines
12
, a first polysilicon layer of approximately 2,500 Å thick is deposited and then doped with phosphorous. A thick layer of insulating material
16
such as TEOS (tetraethoxy silicate) oxide of approximately 3,000 Å is then deposited on top of the first polysilicon layer. By using standard photomasking processes, the two layers are etched by a plasma etching technique as a stack. After LDD implants are made in the silicon substrate, oxide spacers are formed on the polysilicon gate structure by depositing a thick layer of TEOS oxide of approximately 2,000 Å and then plasma etching. Gates
12
and
14
are thus formed and covered by a thick insulating layer
16
of oxide. A source and drain mask is then applied for an ion implantation process to form the source and drain regions in the silicon substrate.
In the next fabrication step, photomasking is used to form window openings for the cell contact and plasma etching is used to remove any native oxide layer on the silicon substrate. A second polysilicon layer
22
of approximately 3,500 Å is then deposited and patterned by a photomask to form the lower electrode of the stacked capacitor
20
. A dielectric layer
24
of a composite film of oxide-nitride-oxide (ONO) is then deposited as the dielectric layer for the capacitor. The total thickness of the ONO composite film is approximately 70 Å. The ONO composite film can be formed by using a thin layer of native oxide as the first oxide layer, depositing a thin nitride layer on top and then oxidizing the nitride layer to grow a top oxide layer. To complete the fabrication of the stacked capacitor, a third polysilicon layer
28
of approximately 2,000 Å thick is. deposited on top of the dielectric layer and then doped and patterned by a photomask to form an upper electrode. After the formation of the stacked capacitor, peripheral devices can be formed by masking and ion implantation, followed by the formation of a bit line
28
of a polysilicon/metal silicide material. A thick insulating layer
32
of BPSG or SOG is then deposited over the capacitor and reflowed to smooth out the topography and to reduce the step height. Other back-end-processes such as metalization to form metal lines
34
are used to complete the fabrication of the memory device
10
.
The stacked capacitor
10
shown in
FIG. 1
has been successfully used in 16 Mb DRAM devices. However, as device density increases to 256 Mb or higher, the planar surface required for building the conventional stacked capacitors becomes excessive and can not be tolerated. Furthermore, the topography of the device formed in
FIG. 1
requires a difficult planarization process to be performed on the DRAM device. For instance, a reliable method of chemical mechanical polishing (CMP) can not be used.
It is therefore an object of the present invention to provide a method for making stacked capacitor DRAM cells that does not have the drawbacks or shortcomings of the prior art methods.
It is another object of the present invention to provide a method for making stacked capacitor DRAM cells that is compatible with a chemical mechanical polishing method to achieve planarization.
It is a further object of the present invention to provide a method for making stacked capacitor DRAM cells that can be readily adapted in ultra high density devices such as the sub 0.18 micron technology.
It is another further object of the present invention to provide a method for making stacked capacitor DRAM cells by first depositing at least two layers of interpoly-oxide on top of a pre-processed silicon wafer.
It is yet another object of the present invention to provide a method for making stacked capacitor DRAM cells by depositing a silicon nitride layer on a thick oxide layer such that cell contacts can be formed in the oxide layer.
It is still another object of the present invention to provide a method for making stacked capacitor DRAM cells by forming polysilicon plugs in a thick oxide layer by using a nitride layer as etch stop.
It is still another further object of the present invention to provide a method for making stacked capacitor DRAM cells by first forming polysilicon plugs and then crown-shaped lower and upper polysilicon electrodes on top of the plugs.
It is yet another further object of the present invention to provide a method for making stacked capacitor DRAM cells by using a thin ONO composite film as the dielectric layer for the capacitor.
It is still another further object of the present invention to provide a method for forming stacked capacitor DRAM cells by depositing a rugged polysilicon layer on top of the lower polysilicon electrode prior to the deposition of the dielectric layer such that the capacitance of the stacked capacitor can be improved.
SUMMARY OF THE INVENTION
In accordance with the present invention, a stacked capacitor DRAM cell can be formed by first forming a polysilicon plug and then depositing two polysilicon layers and a dielectric layer making electrical connection to the plug forming a crown-shaped capacitor.
In a preferred embodiment, a method for making a stacked capacitor DRAM cell can be carried out by first

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