Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1997-08-14
1999-09-28
Everhart, Caridad
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438619, 438622, 438624, 438633, 438631, H01L 21469
Patent
active
059603119
ABSTRACT:
A method of forming a thick interlevel dielectric layer containing sealed voids, formed in a controlled manner, over a substantially planar surface in semiconductor device structure, and the semiconductor structure formed according to such a method. The sealed voids are used to reduce interlevel capacitance. A plurality of metal signal lines are formed over a globally planarized insulator. A thick layer of first conformal interlevel dielectric is deposited over the metal signal lines and over the intermetal spacings formed between the metal signal lines. Because of the thickness, flow properties, and manner of deposition of the interlevel dielectric and the aspect ratio the intermetal spacings, voids are formed in the first conformal interlevel dielectric, in the intermetal spacings. This interlevel dielectric is then etched or polished back to the desired thickness, which exposes the voids in the wider intermetal spacings, but does not expose voids in the narrower intermetal spacings. An etchback may be chosen so that all voids are exposed. The exposed voids are filled with a flowable dielectric which can be then etched back to leave the flowable dielectric in the exposed voids. A second conformal interlevel dielectric layer is formed over the first conformal interlevel dielectric to further bury the sealed voids, insuring that they do not get exposed in further process steps. The second conformal interlevel dielectric may be formed in a thin layer to allow the flowable dielectric to remain near the top of the interlevel dielectric structure to reduce the possibility of poisoned vias.
REFERENCES:
patent: 5114530 (1992-05-01), Rao et al.
patent: 5252520 (1993-10-01), Kocmanek et al.
patent: 5268193 (1993-12-01), Beuhler et al.
patent: 5279865 (1994-01-01), Chebi et al.
patent: 5344797 (1994-09-01), Pai et al.
patent: 5512775 (1996-04-01), Cho
patent: 5559055 (1996-09-01), Chang et al.
patent: 5621241 (1997-04-01), Jain
patent: 5641712 (1997-06-01), Grivna et al.
patent: 5691565 (1997-11-01), Manning
patent: 5691573 (1997-11-01), Avanzino et al.
Ting, Chiu et al., "A Strategy to Accelerate the Implementaion of Low KILD Materials In ULSI Interconnections," in Advanced Metallization for ULSI Applications in 1994, Roc Blumenthal and Guido Janssen, eds. pp. 351-360.
Research Disclosure, No. 303, May, 1990, "Low Temperature Planarized Pre-Metal Passivation".
Balasinski Artur P.
Li Ming M.
Singh Abha R.
Everhart Caridad
Galanthay Theodore E.
Jorgenson Lisa K.
STMicroelectronics Inc.
Thoma Peter J.
LandOfFree
Method for forming controlled voids in interlevel dielectric does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for forming controlled voids in interlevel dielectric, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming controlled voids in interlevel dielectric will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-715323