Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-12-28
2001-06-26
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S301000, C438S306000, C438S976000
Reexamination Certificate
active
06251736
ABSTRACT:
TECHNICAL FIELD
This invention relates to an improved process for manufacturing a MOS transistor in an integrated semiconductor substrate, and more specifically to a process for manufacturing a transistor use in forming non-volatile, contactless, memory cells integrated in electrically programmable EPROM or Flash EPROM matrices.
BACKGROUND OF THE INVENTION
The invention relates, particularly but not exclusively, to a process for manufacturing MOS transistors for use in forming non-volatile memory cells, specifically cells which are integrated in electrically programmable EPROM or Flash EPROM matrices of the contactless type and having a so-called “tablecloth” or cross-point structure, and the description herein below makes reference to this field of application for convenience of explanation. Discussion of steps or devices well known to those skilled in the art has been abbreviated or eliminated for brevity.
Integrated semiconductor EPROM or Flash EPROM electronic memory devices include a large number of memory cells organized into a matrix; that is, cells that are arranged into rows or word lines, and columns or bit lines. Each individual non-volatile memory cell is made from an MOS transistor having a floating gate electrode located above a channel region, i.e., the floating gate shows a high d.c. impedance to all the other terminals of the same cell and to the circuit in which the cell is incorporated.
The cell also has a second electrode, referred to as the control gate, which is driven by appropriate control voltages. Other electrodes of the transistor are the conventional drain, source and body terminals.
In recent years, considerable effort has been made to provide memory devices of higher circuit density. This has led to the development of electrically programmable non-volatile memory matrices of the contactless type, having a so-called “tablecloth” or cross-point structure. One example of a matrix of this kind and its fabrication process is disclosed in European Patent No. 0 573 728 to this Applicant, and hereby incorporated by reference.
In matrices of this type, the memory cells have source and drain regions formed in the substrate by continuous parallel diffusion strips, known as the bit lines, substantially coincident with the matrix columns. In memory matrices of conventional structure this function is served by metal strips connecting individual contacts formed in the drain regions of the cells in one column.
A contactless matrix requires virtual ground circuitry for reading and programming operations. However, the savings in circuit area afforded by such a structure is remarkable, allowing approximately of one order of magnitude higher number of contacts to be provided.
Another reference for this kind of circuit architectures is an article “Alternate Metal Virtual Ground (AMG)—A new Scaling Concept for Very High Density EPROM's”, by Boaz Eiten, IEEE, August 1991, Vol, 12, No. 8.
In this type of a virtual ground matrix, multiple layer parallel strips are defined which include a layer of gate oxide, a first polysilicon layer, an interpoly dielectric layer, and a capping polysilicon layer known as the Poly Cap. These strips form the gate electrodes of the memory cells.
In openings between the various gate electrodes, an implantation, e.g., of arsenic where the substrate is of the P type, is performed to provide the source and drain region diffusion (bit lines).
At this stage of the process, the gate electrodes, which are located between previously exposed bit lines, are sealed to permit the implanting steps. An oxidation step allows the dopant to be diffused under the gate electrodes.
This technique makes the length of the channel region quite difficult to control, where the cell size is small, especially those sized less than 0.4-0.5 &mgr;m. The actual length of the channel region of a MOS transistor is dependent on: the size of the gate electrode, itself dependent on photolithography and etching operations on polysilicon layers; implantations in the channel region controlling the cell performance in terms of threshold voltage and current; and the lateral diffusion of the source/drain regions due to the thermal treatments to which the semiconductor is subjected after the implanting step.
SUMMARY OF THE INVENTION
Embodiments of the present invention provide an improved process for manufacturing MOS transistors, e.g., as incorporated to electronic memory devices integrated in a semiconductor and organized into virtual ground cell matrices, whereby transistors can be formed with a longer channel than in prior art devices.
Embodiments of the invention implant the source/drain regions of the transistor after covering its gate electrode with a dielectric layer, so that the implanted source/drain regions can be kept away from the walls of the gate electrode and the length of the channel region underlying the gate electrode can be more easily controlled throughout the subsequent thermal processing.
Presented is a process for manufacturing a MOS transistor that begins with forming a layer of gate oxide over a semiconductor substrate, and forming a gate electrode over this oxide layer. Then, a layer of covering oxide is formed over the gate oxide layer, the gate electrode, and around the gate electrode. Next a dopant is implanted to provide implanted regions adjacent to the gate electrode, and the semiconductor is subjected to thermal treatments that cause the implanted regions to diffuse into the semiconductor substrate under the gate electrode, and form gradual junction drain and source regions of the transistor.
The features and advantages of a device according to the invention will be apparent from the following description of an embodiment thereof, given by way of non-limitative example with reference to the accompanying drawings.
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Brambilla Claudio
Caprara Paolo
Cereda Sergio Manlio
Elms Richard
Galanthay Theodore E.
Ianucci Robert
Pyonin Adam
Seed IP Law Group PLLC
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