Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-05-07
2001-04-17
Lee, Eddie C. (Department: 2815)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S631000, C438S633000, C438S652000, C438S653000, C438S672000
Reexamination Certificate
active
06218291
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the manufacture of semiconductor devices. More particularly, the present invention is directed to a novel method for forming contact plugs and simultaneously planarizing a substrate surface in integrated circuits.
2. Description of the Related Art
As integrated circuit devices become more complex, greater numbers of interconnect levels are required to connect the various sections of the device. Generally contact vias are formed between interconnect levels to connect one level to another. When multiple layers of interconnects are used in this manner, however, difficulties arise in forming upper interconnect levels and contact vias due to the uneven topographical features caused by the lower interconnect levels. Thus, the topography of interconnect levels affects the ease of manufacturing of the integrated circuit device.
The uneven topographical features of multiple interconnect levels are caused by forming the various interconnect layers above each other, resulting in the creation of hills and valleys on the surface of the device. Those skilled in the art will recognize it is difficult to get upper interconnect layers to maintain constant cross-sections when crossing over uneven topography. This leads to portions of the interconnect line having a higher current density, leading to electromigration problems and related device failure mechanisms. These step coverage problems can result in voids and other defects in the interconnect signal lines themselves, and in the contact vias formed between interconnect lines.
Examples of other defects in the interconnect signal lines are open-circuits or short-circuits between layers resulting from the uneven topography caused by the various interconnect layers in a multi-layer structure.
Another example of defects in the interconnect signal lines is the use of a conventional method for forming contact plugs in which a very thick layer of insulating material must be grown or deposited on an underlying region (or a semiconductor substrate) to form contact plugs. According to this conventional method, the contact plugs are formed by using a chemical mechanical polishing (CMP) process which is performed immediately after a conductive layer is deposited filling up contact holes or vias formed through the very thick insulating layer. The insulating layer must be made very thick to accommodate the CMP process for forming the contact plugs. When contact holes or vias are formed through the very thick insulating layer, the aspect ratio of the holes or vias is increased. This leads to two other defects. First, voids may be generated when a conductive layer is deposited on the very thick insulating layer filling up the contact holes or vias. Second, the CMP processing time is increased since the insulating layer is very thick.
Therefore, it would be desirable to provide a method for forming contact vias which are free of voids and other defects, and which result in a more planar topography. It is also desirable that such a method not significantly increase the complexity of the manufacturing process.
SUMMARY OF THE INVENTION
The present invention is directed toward providing a method for forming contact plugs in an integrated circuit which reduces the incidence of defects caused by step coverage problems. A feature of the present invention is the formation of a contact plug which results in a more planar topography. Another feature of the present invention is the formation of a contact plug in which the aspect ratio of a contact hole or via formed through an insulating layer is reduced.
Briefly, in accordance with one aspect of the present invention, a method is provided for forming contact plugs in an integrated circuit. Initially, a conductive structure is formed on a semiconductor substrate having a plurality of diffusion regions therein. A first insulating layer is formed over the semiconductor substrate including the conductive structure. The first insulating layer has a higher step at a first region where the conductive structure is formed in a group than at a second region where the conductive structure is not formed. The first insulating layer is etched using a contact hole forming mask to form a contact hole. A conductive layer is formed on the first insulating layer, filling up the contact hole. The conductive layer is etched until an upper surface of the first insulating layer is exposed. A second insulating layer is formed over the first insulating layer. The contact plug is formed and a substrate surface is simultaneously planarized by planarization-etching the second and first insulating layers, and leaving a part of the second insulating layer in the second region. Before formation of the conductive layer, a barrier layer may be further formed on the first insulating layer, both sidewalls and bottom of the contact hole. Also, before formation of the conductive structure, an oxide layer may be further formed between the conductive structure and the semiconductor substrate.
Briefly, in accordance with another aspect of the present invention, there is provided a method for forming a contact plug in an integrated circuit. The method includes forming a conductive structure on a semiconductor substrate. The method further includes forming a first insulating layer over the semiconductor substrate and the conductive structure. The first insulating layer has a greater height in a first region where the conductive structure is formed than in a second region where the conductive structure is not formed. The method further includes etching the first insulating layer to form a contact hole. The method further includes forming a conductive layer on the first insulating layer and in the contact hole. The method further includes etching the conductive layer until an upper surface of the first insulating layer is exposed. The method further includes forming a second insulating layer over the first insulating layer. The method further includes planarization-etching the second and first insulating layers to form a contact plug and to planarize the second and first insulating layers.
Briefly, in accordance with another aspect of the present invention, there is provided an integrated circuit. The integrated circuit includes a conductive structure, a first insulating layer, a conductive material, and a second insulating layer. The conductive structure is on a semiconductor substrate. The first insulating layer is formed on the semiconductor substrate and the conductive structure, and the first insulating layer has a greater height in a first region where the conductive structure is formed than in a second region where the conductive structure is not formed. There is a contact hole formed in the first insulating layer, and the conductive material fills at least part of the contact hole to form a contact plug. The second insulating layer is formed on the first insulating layer, and the second insulating layer is planarization-etched to planarize the contact plug and the second and first insulating layers.
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Hong Seok-Ji
Yoon Bo-Un
Lee Eddie C.
Richards N. Drew
Samsung Electronics Co,. Ltd.
The Law Offices of Eugene M. Lee P.L.L.C.
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