Method for forming contact holes and semiconductor device...

Details Method for forming contact holes and semiconductor device... Method for forming contact holes and semiconductor device...

1999-10-14

2002-01-01

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

Reexamination Certificate

active

06335275

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention generally relates to a semiconductor device and its fabrication processes, and in particular the present invention relates to a method for forming contact holes.
BACKGROUND OF THE INVENTION
In fabrication of semiconductor devices, contact holes have been formed using etching technology. In an etching process, a resist pattern is formed on a surface of a semiconductor substrate, then an oxide layer or polysilicon layer is etched using the resist pattern as a mask. These days, the major techniques for the etching process are dry etching and wet etching.
In a dry etching process, a particular layer is etched with a predetermined etching gas. In a wet etching process, a particular layer is etched with a chemical solution. In an etching process using a strip-shaped resist pattern as an etching mask, when the etching process progresses under the etching mask, a given pattern is formed to have a narrower width than that of the resist pattern (designed width). In an etching process using a groove-shaped resist pattern as the etching mask, when the etching process progresses under the etching mask, a given pattern is formed to have a wider width than that of the resist pattern (designed width). This kind of etching is called isotropic etching. In contrast, etching that does not progress under an etching mask is called anisotropic etching.
In a reactive ion etching process, a reaction gas is introduced into an etching chamber, which is under vacuum. When RF-power, for example, of 13.56 MHz, is applied to the reaction gas, plasma is generated in the etching chamber. In the etching chamber, active atoms and molecules, such as ions and radicals, are generated. For example, when CF
4
gas is introduced into the etching chamber, positive ions, such as CF
3
+
and CF
2
+
, and radicals, such as F* and CF*, are generated in response to the plasma.
A semiconductor substrate is put on a stage in the etching chamber. When a bias is applied to the semiconductor substrate, the electric field accelerates the positive ions so as to impact upon the surface of the semiconductor substrate. With the impact of the positive ion, the surface of the semiconductor substrate is decomposed. The decomposed particles react easily with radical of F* and CF*, so the etching process progresses quickly. The ion impact progresses in a vertical direction to the semiconductor substrate, so that the reactive ion etching is recognized as anisotropic.
Recently, contact holes have been formed using the above described anisotropic etching technique. According to a conventional method, an oxide layer is deposited on a silicon substrate by a CVD (Chemical Vapor Deposition) technique. Subsequently, a polysilicon layer is deposited over the entire surface of the structure, and then a resist pattern is formed on the polysilicon layer. Next, the polysilicon layer is etched using the resist pattern as an etching mask to form an opening (base of a contact hole) therein. The etching process is carried out using a halogen system gas, such as Cl
2
or HBr.
Next, the resist pattern is removed, and then another polysilicon layer is deposited over the entire surface of the structure. The polysilicon layer is etched by an anisotropic etching process to form a sidewall of polysilicon inside the opening. The sidewall is be used as a spacer or mask in the next step.
Subsequently, the CVD oxide layer is etched by an anisotropic etching process using the polysilicon layer and sidewall as a mask to form a contact hole.
According to the above-described conventional method, the contact hole is tapered, having a wider opening area at the top and a narrow opening area at the bottom because the etching process is of anisotropic etching. That is because the polysilicon layer and sidewall are etched at an etching rate determined according to the ratio of etching rates between the CVD oxide layer and the polysilicon layer. The sidewall is etched while the CVD oxide layer is etched, so that the contact hole is tapered.
According to another conventional method, an oxide layer is deposited on a silicon substrate by a CVD (Chemical Vapor Deposition) technique. Next, a polysilicon layer is deposited over the entire surface of the structure by a CVD process, and then a resist pattern is formed on the polysilicon layer. Next, the polysilicon layer is etched using the resist pattern as an etching mask to form an opening (base of a contact hole) therein. The etching process may be anisotropic etching using a halogen system gas, such as Cl
2
or HBr.
Subsequently, the resist pattern is removed, and then a polysilicon layer is deposited over the entire surface of the structure. The polysilicon layer is etched by an anisotropic etching process to form a sidewall of polysilicon inside the opening. The sidewall is used as a spacer or mask in the next step. The CVD oxide layer is etched by an anisotropic etching process using the polysilicon layer and sidewall as a mask to form a contact hole.
According to the above-described conventional method, the contact hole is tapered, having a wider opening area at the top and a narrow opening area at the bottom. In this method, the polysilicon layer is etched to have a tapered cross section.
In recent years, as contact holes have been designed to be smaller, exhaustion characteristic of holdup gas becomes lower. Resist reaction products, including constituent elements of the resist layer, and etching reaction products, including constituent elements of the etching gas, holdup easily in the contact hole. Such reaction products are re-attached on the inside wall of the contact hole, so that the contact hole is overprotected.
Generally, a halogen system gas including Cl or Br does not react well with silicon, so that a higher bias is applied to the Cl ions and Br ions in the plasma to accelerate such ions. As a result, the ions are injected vertically to a polycrystalline silicon layer, and therefore, impact power of the ions is increased. Cl radicals and Br radicals, attached to the silicon layer, react with the silicon with energy received from the injected ions, and are removed from the substrate. In this case, the polysilicon layer is etched with the high-energy ions in a highly anisotropic manner, and at the same time, the ions are also injected onto the resist pattern.
Resist system products, hereinafter called “resist system sputter products”, are generated in response to an impact of the ions. Etching reaction products on the silicon layer are deposited on the inside wall of the contact hole. The deposited products function as a mask in the etching process, and therefore, it can be understood that the opening (base of the contact hole) formed in the polysilicon layer is easily tapered. The shapes of contact holes may vary even though the contact holes are formed under the same etching process condition. This means that it is difficult to shape contact holes uniformly.
After a contact hole is formed in the CVD oxide layer, the polysilicon layer and sidewall are completely removed. Next, a titanium nitride layer is formed on the CVD oxide layer, and then a tungsten layer is formed on the titanium nitride layer by a CVD process to form a laminated layer. Subsequently, an etching back process is carried out upon the entire surface of the structure, and a tungsten plug is etched at a center (bottom), so that even the silicon substrate may be etched.
Next, an aluminum layer is deposited on the surface of the structure. In this process, a cavity is formed in the tungsten plug. Next, the aluminum layer is patterned. After that, an insulating layer (interlayer insulator film) and a passivation film are formed on the aluminum layer. The cavity is not filled with the insulating material. In later processes, such as thermal treatment or burn-in treatment after assembly, air in the cavity expands, and therefore, the tungsten plug may be broken. Such a problem results in a defective semiconductor device.
OBJECTS OF THE INVENTION
Accordingly, an object of the present inve

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