Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-12-27
2003-11-25
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S196000, C438S207000, C438S221000, C438S435000, C438S692000
Reexamination Certificate
active
06653194
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for forming a contact hole in a semiconductor device, and more particularly to a method for forming a contact hole which can prevent an isolation region from being damaged because there is little overlap margin for a contact hole in the active region, when a contact hole is formed over both an active region and an isolation region, i.e., when a borderless contact hole is formed.
2. Description of the Prior Art
According to the design of the structure of a logic device, it is necessary to form a contact hole on a gate or active region only. However, as the dimensions of a logic device are reduced, an overlap margin for a contact hole gradually decreases in the active region. As a result, due to a misalignment phenomena caused from a lithography process, a contact hole, which is meant to be formed only in an active region, may be sometimes be partially formed in an isolation region beyond the border of the active region. Such a contact hole is called as “borderless contact hole.”
In the conventional process of manufacturing semiconductor devices, it is common to form a contact hole by performing dry etching using plasma formed by activating a ‘C
x
F
y
+O
2
’ gas, wherein the ‘C
x
F
y
’ means a gas selected from a group consisting of CF
4
, C
2
F
6
, C
4
F
8
, C
5
F
8
, etc., or a combination thereof. If desired, CHF
3
, Ar or the like may be added to that gas or the combination.
Polysilicon or silicide employed for forming a gate or active region has a characteristic of being scarcely etched by such plasma. In such a case, no damage is caused while a contact hole is being etched. However, a silicon oxide-based material (SiO
2-&bgr;
) employed for forming an isolation region has a characteristic of being easily etched by such plasma. Therefore, a problem arises in that an isolation region is deeply and sharply hollowed out in the process of forming a borderless hole.
FIG. 1
is a drawing for illustrating the problematic situation when a contact hole is formed without using an etch-stop layer. In the drawing,
1
designates a silicon substrate,
2
designates a shallow trench isolation (STI),
3
designates a well,
4
designates a gate oxide layer,
5
designates a gate (polysilicon),
6
designates a silicide layer,
7
designates a spacer,
8
designates a source,
9
designates a drain,
10
designates an interlayer insulation layer, and
11
designates a contact hole.
As the dimensions of logic devices are reduced, the overlap margin for a contact hole decreases in the active region. If such an overlap margin for a contact hole is insufficient in an active region, the contact hole, which is meant to be formed only in the active region, is formed into an isolation region, beyond the border of the active region. As a result, a problem is caused in that the isolation region is deeply and sharply hollowed out, as shown in the drawing. If the isolation region is damaged in the process of forming a contact hole like this, leakage current or deterioration of the properties is caused in a resulting semiconductor device, thereby causing problems in operation of the device.
Therefore, in order to solve this problem, a contact hole is formed using an etch-stop layer in a conventional semiconductor device manufacturing process, which will now be sequentially described with reference to FIG.
2
.
Referring to
FIG. 2
a
, a predetermined thickness of a pad oxide layer (SiO
2
)
22
is deposited on a silicon substrate
21
, and then a predetermined thickness of a silicon nitride layer (Si
3
N
4
)
23
is deposited on the pad oxide layer
22
. Herein, the deposited silicon nitride layer
23
is used as a polish-stop layer when an oxidation material formed in a subsequent step for filling a trench is planarized using chemical mechanical polishing (CMP) process.
The pad oxide layer
22
serves as a buffer layer for alleviating the mechanical stress influencing on the silicon substrate
21
; stress which are induced by the silicon nitride layer
23
having been deposited on the pad oxide layer
22
. The thickness of the pad oxide layer
22
and the thickness of the silicon nitride layer
23
may be varied depending on the type of process employed, wherein the pad oxide layer
22
is applied to a thickness of about 70 Å to 200 Å and the silicon nitride layer
23
is applied to a thickness of about 500 Å to 1500 Å.
Next, after a photoresist layer
24
is coated on the silicon nitride layer
23
, a pattern of STI (shallow trench isolation) is formed by exposing and developing the photoresist layer
24
.
Then, the silicon nitride layer
23
and the pad oxide layer
22
are completely etched by dry etching using activated plasma. Activated gases of plasma may be varied depending on the type of employed process. In general, however, a gas formed by mixing C
x
F
y
, H
o
H
p
F
q
, Ar, etc., in a predetermined ratio is mainly used for generating plasma. If the dry etching is continuously performed using activated plasma, a trench
25
is formed in the silicon substrate
21
. When forming the trench
25
in the silicon substrate
21
, plasma is generated mainly using a gas formed by properly mixing Cl
2
, HBr, N
2
, Ar, etc. After the silicon substrate
21
is etched to a desired depth, the remaining photoresist is completely removed.
Thereafter, the trench
25
formed in the step shown in
FIG. 2
c
is filled with an oxide layer (SiO
2
)
26
deposited using a plasma enhanced chemical vapor deposition (PECVD) process. Here, one or more stepped portions may be formed in the top surface of the deposited oxide layer, which reflects the surface topology of a layer laid under the oxide layer.
The top surface of the oxide layer
26
deposited in the step of
FIG. 2
a
is planarized and the oxide layer
26
deposited on the silicon nitride layer
23
′ is removed, using CMP process, as shown in
FIG. 2
b
. At this time, the silicon nitride layer
23
′ serves as a polish-stop layer to prevent the silicon substrate
21
from being polished. During this step, the silicon nitride layer
23
′ is partially polished and thus its thickness is reduced.
Referring to
FIG. 2
c
, the remaining silicon nitride
23
′ is removed using a phosphoric acid aqueous solution (H
3
PO
4
). If the concentration and temperature of the phosphoric acid aqueous solution of are properly controlled, the etch selectivity ratio of a typical SiO
2
layer to the silicon nitride
23
′ can be made to exceed about 1:50. Therefore, using the phosphoric acid aqueous solution, it is possible to completely remove the remaining silicon nitride film
23
′ without damaging the oxide layer
26
filled in the trench
25
.
Referring to
FIG. 2
d
, a well
27
, a gate
28
, a spacer
29
, a source/drain
30
, and a silicide layer
31
are formed in accordance with the method of manufacturing a typical logic device.
Next, a silicon nitride (Si
3
N
4
) layer
32
is thinly deposited on the entire surface to a thickness of about 200 Å to 400 Å. The deposited silicon nitride layer
32
serves as an etch-stop layer in a subsequent step for forming a contact hole.
Referring to
FIG. 2
e
, after an interlayer oxide film
33
is deposited, the top surface of the interlayer oxide film
33
is planarized using chemical mechanical polishing process. In general, the interlayer oxide film
33
has a thickness of about 7,000 Å to 9,000 Å after the planarization is completed. In most cases, even if the thickness of the interlayer oxide film
33
is controlled to be constant and its planarization is completed, some variations in thickness exist in the interlayer oxide film, due to incompleteness of deposition and subsequent polishing steps.
Next, a photoresist layer
34
is coated on the interlayer oxide film
33
, exposed and developed to pattern a form of contact hole.
Referring to
FIG. 2
f
, the interlayer oxide film
33
is etched using plasma generated by activating a ‘C
x
F
y
+O
Fourson George
Hynix / Semiconductor Inc.
Pham Thanh
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