Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-08-04
2001-02-27
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S246000, C438S514000, C438S523000, C438S533000, C438S557000, C438S558000, C438S561000, C438S637000
Reexamination Certificate
active
06194309
ABSTRACT:
This application relies for priority upon Korean Patent Application No. 98-32460, filed on Aug. 10, 1998, the contents of which are herein incorporated by reference in their entirety.
FIELD OF THE INVENTION
The present invention relates to a method for fabricating a semiconductor device. More particularly the present invention relates to a method for forming a contact of a semiconductor device.
BACKGROUND OF THE INVENTION
As DRAM (dynamic random access memory) devices have become more finely structured, both the area of such devices and the diameter of contacts used on these devices have been reduced. Despite a reduction of both the area and the diameter in the horizontal direction, however, this fine structure does not effect the structural characteristics of a DRAM in the vertical direction. Accordingly, contacts must be both fine and long.
Referring to
FIG. 1
, a device isolation region (not shown) defining an active region and an inactive region is formed in a semiconductor substrate
10
. A first conductive layer (not shown), a second conductive layer (not shown), and a gate mask
16
are formed over a semiconductor substrate
10
in the active region with a gate oxide layer (not shown) interposed between these layers and the substrate
10
. The first and second conductive layers are then etched using the gate mask
16
as an etching mask to form a gate electrode of a double layer structure including first and second gate electrode portions
12
and
14
.
After or before the formation of the insulating layer spacer
16
, impurity ions are implanted to form a source/drain region (not shown) in the semiconductor substrate
10
outside of the area covered by the gate electrode
12
and
14
. A first interlayer insulating film
20
is then formed over the semiconductor substrate
10
and the gate electrode
12
and
14
.
The first insulating film
20
is penetrated by a first contact hole
21
, and the resulting contact hole
21
is filled with a conductive material to form a contact pad
22
that is electrically connected to the source/drain region.
A second interlayer insulating film
24
, including an embedded bit line
26
, is then formed over the first interlayer insulating film
20
. The second insulating film
24
is etched to form a second contact hole
28
that exposes a top surface of the contact pad
22
. A silicon nitride layer spacer
30
is then formed on the sidewalls of the contact hole
28
.
The second contact hole
28
is then filled with a conductive material to form a buried contact (BC)
32
that electrically connects a lower capacitor electrode to the contact pad
22
. In order to make this electrical connection to the buried contact
32
, a conductive layer (not shown) is formed over the second interlayer insulating film
24
. The conductive layer is then patterned to form the lower capacitor electrode
34
.
In the DRAM device of a capacitor over bit line (COB) structure, as described above, the buried contact
32
becomes fine and long. Furthermore, as shown in
FIG. 1
, the spacers
30
formed on the sidewalls of a contact hole may reduce the contact area between the contact pad
22
and the buried contact
32
. As a result, the resistance between the contact pad
22
and the buried contact
32
increases, thereby slowing down the operation speed of the DRAM and potentially making an electrical open circuit, if the resistance is high enough.
SUMMARY OF THE INVENTION
It is therefore a principal feature of the present invention to provide a method for forming a contact capable of reducing the resistance between a contact pad and a buried contact.
In accordance with the present invention, a method is provided for forming a contact of a semiconductor device in which a conductive layer pattern is electrically connected to a semiconductor substrate and is buried in a first interlayer insulating film formed over both the semiconductor substrate, and the conductive layer pattern, which has the same level in height as the first interlayer insulating layer. This method comprises forming a second layer interlayer insulating film over the semiconductor substrate, including the conductive layer pattern, forming a contact hole by etching the second interlayer insulating film down to a top surface of the conductive layer pattern, using a contact formation mask, isotropically etching the conductive layer pattern through the contact hole to increase the surface area of an exposed portion of the conductive layer pattern, and filling the contact hole with a conductive material, to form a contact plug electrically connected to the conductive layer pattern.
The method may further comprise doping an impurity ion into the conductive layer pattern through the contact hole to increase at least the impurity concentration of the exposed portion of the conductive pattern, wherein the doping is performed after the isotropic etching. The impurity ion is preferably doped through one of an ion implanting process or a thermal doping process.
The method may further comprise forming an insulating layer having an etching selectivity with respect to the second interlayer insulating film over the interlayer insulating film and in the contact hole, after formation of the contact hole, isotropically etching the second insulating layer down to a top surface of a conductive pattern underlying the contact hole, to form a spacer on sidewalls of the contact hole, and etching a surface of the exposed conductive layer pattern to suppress etching damage of the surface of the conductive layer pattern and to remove etching impurities on the conductive layer pattern, wherein the surface of the conductive layer pattern is overetched to form a recess region.
The conductive pattern may comprise polysilicon; the interlayer insulating film may comprise an oxide; and the insulating layer may comprise Si
3
N
4
.
In the alternative, a method for forming a contact of a semiconductor device, is provided, comprising forming a conductive layer pattern over a semiconductor substrate, forming an interlayer insulating film over the conductive layer pattern, forming a contact hole in the interlayer insulating film, etching the conductive layer pattern through the contact hole to increase the surface area of an exposed portion of the conductive layer pattern, and filling the contact hole with a conductive material, to form a contact plug electrically connected to the conductive layer pattern.
In a novel method according to the present invention, an interlayer insulating film is etched to form a contact hole. The conductive layer pattern exposed through the contact hole is isotropically etched, thereby increasing the contact area between a contact hole and a contact plug formed by filling conductive material in the following process. Ions is implanted into the conductive layer pattern through the contact hole. In this way, it is therefore possible to increase the contact area between a contact pad and a contact plug (i.e., the interface between the buried contact and the contact pad) and to increase the surface impurity concentration of the contact pad contacted with the buried contact. As a result, the contact resistance between the buried contact and the contact pad can be reduced.
REFERENCES:
patent: 5252517 (1993-10-01), Blalock et al.
patent: 5985762 (1999-11-01), Geffken et al.
Booth Richard
Jones Volentine, L.L.C.
Nguyen Ha Tran
Samsung Electronics Co,. Ltd.
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