Method for forming complementary wells and self-aligned trench w

Details Method for forming complementary wells and self-aligned trench w Method for forming complementary wells and self-aligned trench w

1997-06-30

1999-09-21

Monin, Jr., Donald L.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438223, 438229, 257372, 257374, H01L 2976

Patent

active

059565837

ABSTRACT:
An integrated circuit includes a plurality of CMOS transistors formed in a monocrystalline substrate. Within the substrate is a plurality of complementary spaced pairs of a p-well region and a n-well region. Between each well region, each of which has a source, gate, and drain, is a self-aligned trench filled with semiconductor material. A method of fabricating a field effect transistor entails a first step of forming a layer of first insulative material over a monocrystalline substrate. Next, a layer of semiconductor material is formed over the first insulative material. A p- or n-well masking layer is formed over the semiconductor layer and patterned to expose a first portion of the underlying semiconductor layer. A first dopant of one polarity is implanted in the region of the substrate aligned with the semiconductor layer first portion, which is then converted into a second insulative material. The masking layer is removed, thereby exposing the remaining portion of the semiconductor layer. A second dopant of opposite polarity to the first dopant is then implanted into the remaining portion. Removal of the first portion and the exposed remaining portion of the semiconductor material exposes a step of semiconductor material, which, along with a portion of the substrate aligned with the step, is subsequently removed to form a trench. The trench is filled with a second semiconductor material.

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