Method for forming compact memory cell using vertical devices

Details Method for forming compact memory cell using vertical devices Method for forming compact memory cell using vertical devices

1996-10-24

1999-03-23

Tsai, Jey

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438254, 438268, H01L 218242

Patent

active

058858644

ABSTRACT:
An exemplary embodiment of the present invention includes a memory cell in a semiconductor device, comprising a substantially vertical-gated, access transistor having its gate electrode surrounding a pillar portion of a silicon material, a first source/drain electrode in an upper portion of the pillar portion and a second source/drain electrode in a silicon material extending substantially horizontally about the base of the pillar portion; and a storage capacitor having its storage electrode connecting to the first source/drain electrode. The structure of the storage capacitor may configured as desired which includes a stacked capacitor structure or a cylindrical capacitor structure.

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IEEE Transactions on Electron Devices, vol. 39, No. 8, Aug. 1992 pp. 1876-1881 -"Numerical Analysis of a Cylindrical Thin-Pillar Transistor (CYNTHIA)".

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