Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-12-19
2004-08-24
Le, Dung A. (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S254000, C438S637000, C438S700000
Reexamination Certificate
active
06780709
ABSTRACT:
BACKGROUND
1. Technical Field
Methods for forming charge storage nodes are disclosed, and more particularly, methods for forming charge storage nodes which prevent the bridge between cells and maximize the hole size of a cell forming portion to thus improve the properties of the devices and increase product yield by depositing an oxide film having a predetermined thickness and forming a contact hole in order to fill the hole of a notch type generated by the etching difference between a damaged sacrificial oxide film and an oxide film for capacitor formation deposited thereon after enlarging the hole size by washing and dipping processes before the formation of the charge storage node.
2. Description of the Related Art
Recently, with high integration of semiconductor devices, semiconductor memory devices such as a DRAMs (Dynamic Random Access Memory) demand a capacitance larger than a predetermined capacity to obtain the desired operational characteristics. Also, with high integration, as the area per unit cell decreases, the devices must occupy a smaller surface area while securing a large capacitance.
FIG. 1
is a photograph showing the problem of a charge storage node according to the conventional art.
In a conventional method of forming a charge storage node (not shown), first, a predetermined substructure is formed on a semiconductor substrate. A planarization process is carried out to form a charge storage node. An etching stop film and sacrificial oxide film of a predetermined thickness are formed sequentially. Next, a first contact hole is formed on the portion in which the charge storage node is to be formed by masking and etching processes.
Next, to fill the first contact hole, a doped amorphous silicon film or a polycrystalline silicon film is deposited. Then, second contact hole is formed by etching the front surface, and an oxide film having a predetermined height is deposited. Subsequently, the portion in which the charge storage node is to be formed is patterned by masking and etching processes. Thereafter, a washing process is performed to form the charge storage node.
However, such a conventional method of forming a charge storage node has some defects. As illustrated in
FIG. 1
, the sacrificial oxide film on the upper portion of the etching stop film is damaged in the etchback process of the polysilicon film. Hence, a notch type hole is formed by an etching difference between the sacrificial oxide film and the polysilicon film. This generates a bridge between cells which deteriorates the operational characteristics of the device and causes a reduction in product yield.
SUMMARY OF THE DISCLOSURE
Therefore, a method is disclosed for forming a charge storage node which prevents the bridge between cells and maximizes the hole size of a cell forming portion to thus improve the properties of a device. The disclosed method also increases product yield by depositing an oxide film having a predetermined thickness and forming a contact hole in order to fill the hole of a notch type generated by the etching difference between a damaged sacrificial oxide film and an oxide film for capacitor formation deposited thereon after enlarging the hole size by washing and dipping processes before the formation of the charge storage node.
A disclosed method for forming a charge storage node comprises: carrying out a planarization process for forming a charge storage node on a substrate in which a predetermined substructure is formed and then depositing an etching stop layer and a sacrificial oxide film in order; forming a first contact hole on the resultant material by masking and etching processes; depositing doped amorphous silicon to fill the first contact hole for the charge storage node; forming a second contact hole on the doped amorphous silicon film by an etchback process and then performing a washing process; dipping the second contact hole in a wet etching solution for oxidation for a predetermined time after the washing process; forming an oxide film having a predetermined thickness on the resultant material in which the second contact hole is formed and then opening the first contact hole at the lower portion by performing the etchback process; depositing a polysilicion film having a predetermined thickness on the resultant material in which the first contact hole is opened and then depositing a photoresist at a predetermined thickness; etching the upper portion of the polysilicon film by the etchback process using the photoresist; and removing the photoresist and forming a meta-stable polysilicon film.
Preferably, the washing process is performed using a clean B solution (H
2
SO
4
+H
2
O=4:1) to remove organic substances, a SC-
1
solution (aqueous solution of NH
4
OH and H
2
O
2
) to remove particles and impurities and a HF (hydrofluoric acid) or BOE (buffered oxide etch) solution to prevent the generation of a natural oxide film. The polysilicon film is formed at a thickness ranging from about 100 to about 2000 Å at a pressure ranging from 0.1 to about 300 torr at a temperature ranging from about 450 to about 560° C. using one of gases selected from SiH
4
, Si
2
H
6
, SiH
2
Cl
2
and PH
3
gases.
Preferably, the oxide film forms one of film selected from a HTO (high temperature oxide) film, a LTO (low temperature oxide) film, a PE-TEOS (plasma enhanced tetra ethyl ortho silicate) film, and a LP-TEOS (low pressure tetra ethyl ortho silicate) film. The oxide film is preferably formed by the CVD (chemical vapor deposition) method.
Preferably, the dipping process using the wet etching solution for oxidation is performed for a time period ranging from about 5 to about 300 seconds using the BOE solution with the ratio of about 300:1. The meta-stable polysilicon (MPS) film is formed to a range of about 1.1 to about 2.6 times larger than the polysilicon film.
REFERENCES:
patent: 5766993 (1998-06-01), Tseng
patent: 5907772 (1999-05-01), Iwasaki
patent: 5953609 (1999-09-01), Koyama et al.
patent: 6087212 (2000-07-01), Hirota
Kim Eui-sik
Woo Sang-ho
Hynix / Semiconductor Inc.
Le Dung A.
Marshall & Gerstein & Borun LLP
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