Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-12-23
2001-01-23
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S398000
Reexamination Certificate
active
06177310
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the formation of capacitor of memory cell, and more particularly for using silicon oxide on a silicon substrate layer of silicon wafer for semiconductor device.
2. Description of the Prior Art
Currently, one of the main art for improving DRAM performance could be hemi-spherical grain (HSG) process. In fact, recently Hemi-Spherical Grain (HSG) process is gradually applied to the production technology of High-Density DRAM in practical. Furthermore, HSG process ideally will increase the surface area of silicon layer in order to expand the capacity of DRAM, this issue was presented by some of previous laboratory experience already.
Basically HSG process is firstly to be deposited an alpha-type silicon thin film on the substrate of silicon wafer inside a PCVD furnace at 1 torr and 510° C. to 550° C. Consequentially alpha-Silicon film surface is cleaned using SC-1 wet cleaning and then the native oxide layer is removed by HF dipping. Afterward HSG will grew up in furnace chamber. Firstly, the chamber is pre-heat before loading the wafer into furnace chamber. When wafer is irradiated about 60 seconds, then conducting gas into the chamber. At this step, temperature is arrived about 200° C. to 300° C., then the gas is ceased after about 60 seconds. Thirdly temperature is held at 600° C. The whole treatment time is about 300 seconds at least. The pressure is about 10
−5
torr when conducting the gas. Also, when the gas is not conducted into the chamber, the pressure will be about 10
−8
torrs, also the gas fluid is about 10 sccms.
However, unfortunately hemispherical grain (HSG) process is still not totally desirable because there still is a short road problem, such as FIG.
1
. From
FIG. 1
, it is apparently found that HSG in Portion
1
and HSG in portion
2
are too close so that it will cause bridging problem. On the other hand, it is still necessary to be refined again. According to this consideration, this present invention now submits a brand new preferred method for forming HSG in DRAM structure.
Generally, demand for high-density dynamic random access memory (DRAM) has rapidly increased due to widespread use of electronic equipment. In particular, the increasing popularity of some electronic equipment such as, for example, many kinds of computers are gradually increasing the demand for the large or very large semiconductor memories in this modern century and next coming twenty-one century. Therefore, the advanced manufacture technology for improvement fabrication of DRAM should be urgently need than before.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method is provided for forming a capacitor that substantially existing on the substrate for silicon wafer of semiconductor.
First of all, there is a semiconductor substrate that owns a first dielectric layer formed thereon. The first dielectric layer has a contact opening filled with doped polysilicon to form a stud. Then, a second dielectric layer is formed on the first dielectric layer and the surface of the stud. A silicon oxynitride (SiON) layer can be formed on the second dielectric layer. A photoresist layer is formed on the silicon oxynitride layer to define an area for the capacitor by a ring pattern located over the stud. Portions of the silicon oxynitride layer and the second dielectric layer are etched using the ring pattern of the photoresist layer as an etch mask. Blanket and conformably forming an amorphous silicon layer is carried out on the surface of the silicon oxynitride layer, the first dielectric layer, and the stud, and on the sidewall of the capacitor. A third dielectric layer is formed on the amorphous silicon layer. The third dielectric layer and a portion of the amorphous silicon layer atop of the silicon oxynitride layer are all etched back until the silicon oxynitride layer is exposed. The silicon oxynitride layer is used as an anti-etching layer, therefore the capacitor comprised of the amorphous silicon layer is formed and located within the cylinder. The amorphous silicon layer will be treated to form a hemispherical-grained (HSG) layer on the surface of the amorphous silicon layer. The silicon oxynitride layer is removed, thereby resulting in the capacitor with the hemispherical-grained layer covering only the internal surface of the capacitor while leaving the external surface of the pillar uncovered by the hemispherical-grained layer. Dipping the surface of the second dielectric layer is achieved to comprehensively clean the surface thereof, thereby preventing unwanted connection of the hemispherical-grained layer on the capacitor with the hemispherical-grained layer out of the capacitor.
REFERENCES:
patent: 5989952 (1999-11-01), Jen et al.
patent: 6080619 (2000-06-01), Chien et al.
Chern Horng-Nan
Lin Kuen-Yow
Tsai Jey
United Microelectronics Corp.
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