Method for forming capacitor of a DRAM having a wall...

Details Method for forming capacitor of a DRAM having a wall... Method for forming capacitor of a DRAM having a wall...

2001-02-15

2002-09-24

Trinh, Michael (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S239000, C438S241000

Reexamination Certificate

active

06455371

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to DRAM, and more particularly to a capacitor of a DRAM cell.
2. Description of the Prior Art
A DRAM cell is generally constituted of a metal-oxide-semiconductor (MOS) field effect transistor and a capacitor connected to the MOS field effect transistor. With the increase of an integration density, the occupied area of each memory cell in a plan is decreased. However, the amount of storage capacitance in the limited area of a DRAM cell is very important in application. Recently, a three-dimensional structure has been proposed to provide a stacked capacitor over a bit line (COB), and to increase a height of a storage node electrode constituted of a lower plate of the stacked capacitor.
A DRAM cell with a conventional COB structure is shown in
FIG. 1. A
semiconductor substrate
100
is provided and thereon multitude of gate structure (word line)
120
are formed. Of course, there may be some source/drain regions and isolation device (not shown), such as field oxide, are formed in and on the semiconductor substrate
100
. A tungsten silicide layer
130
is on the gate structures
120
and a first inter-polysilicon dielectric layer (IPD
1
)
110
is deposited on the tungsten silicide layer
130
and the semiconductor substrate
100
. A bit line structure
140
constituted of polysilicon deposited in and on the contact hole in the first inter-polysilicon dielectric layer
110
may be shown. A second inter-polysilicon dielectric layer (IPD
2
)
160
is subsequently deposited on the first inter-polysilicon dielectric layer
110
and the tungsten silicide layer
150
. Furthermore, a multitude of capacitor node structures
170
are constituted of polysilicon in and on the contact holds in both the first and the second inter-polysilicon layer (
110
and
160
).
However, those capacitor node structures
170
are so protrudent that they are susceptible to the following cleaning process and removed out. The removal of the capacitor node structures may result in damages in some characteristics.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method of protecting the capacitor structures of a DRAM cell. The capacitor node structures in a DRAM cell are formed between multitude of wall structures constituted of inter-polysilicon layer.
It is another object of the present invention to provide a method of reducing the removal of the capacitor structures during DRAM manufacture process. The capacitor node structures can be protected from water or mega-sonic flow during cleaning steps.
In the present invention, a method for forming capacitor of a dynamic random access memory cell. The method comprises providing a substrate and the word line structures formed thereon. A first dielectric layer is deposited on the substrate and the word line structures. A first polysilicon layer is deposited to form bit line contacts and bit lines. A second dielectric layer is formed on the first dielectric layer and the bit lines. The partial second dielectric layer is removed to form at least a wall structure in the second dielectric layer. The partial second dielectric layer and partial first dielectric layer are removed to form a capacitor contact opening. A second polysilicon is deposited into the capacitor contact opening and on the wall structure and the second dielectric layer. The partial second polysilicon is removed to form a capacitor node whereby a side-wall of the capacitor node is adjacent to the wall structure.


REFERENCES:
patent: 5389568 (1995-02-01), Yun
patent: 5854106 (1998-12-01), Wu
patent: 6008084 (1999-12-01), Sung
patent: 6255161 (2001-07-01), Lin

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