Method for forming buried plates

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S246000, C438S249000, C438S255000

Reexamination Certificate

active

06706587

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for forming buried plates. In particular, the invention involves the formation of buried plates in trench capacitors of DRAMs by drive-in annealing of hemispherical silicon grain (HSG).
2. Description of the Related Art
In the current process for fabricating semiconductor integrated circuits, particularly the 64 and 256 MB memory chips, deep trenches are widely used to define the storage capacitors. The general structure of a storage capacitor is comprised of a deep trench formed within a doped silicon substrate, a dielectric layer formed on the inner surface of the deep trench, and doped silicon that fills the deep trench. In other words, the doped silicon/dielectric layer/doped silicon structure forms the storage capacitor. In the continuous development of smaller sizes of capacitors, the thickness of the dielectric layer must be decreased to maintain its capacitance. Consequently, voltage of the overall dielectric layer must be greatly reduced to avoid undesired voltage breakdown effect. In order to achieve reduced voltage, a doped area i.e. a buried plate, is formed around the bottom part of the storage capacitor.
An example of current process for forming buried plates in deep trench DRAMs is shown in
FIGS. 1
a
~
1
h
. First, a deep trench
140
is formed in a predetermined position in a semiconductor substrate
100
, wherein a pad stacked layer A is formed on the substrate in advance. The pad stacked layer A comprises a pad oxide layer
130
and a pad nitride layer
120
. Next, a protective layer
110
is formed on the upper sidewalls of the trench, as shown in
FIG. 1
a
. Etching is then carried out to widen the lower portion of the trench not covered by the protective layer to form a bottle trench
150
, shown in
FIG. 1
b.
Next, as shown in
FIGS. 1
c
and
1
d
, an arsenic-doped silicon dioxide glass (ASG) layer
160
and a tetraethylorthosilane (TEOS) layer
170
are formed along the protective layer
110
and the sidewalls and bottom of the bottle trench
150
. Drive-in is then performed to form an inner plate
180
within the sidewalls of the bottle trench, as shown in
FIG. 1
e.
Then, the ASG layer
160
and TEOS layer
170
are removed as shown in
FIG. 1
f
, followed by formation of a hemispherical silicon grain (HSG) layer
190
on the protective layer
110
and the sidewalls and bottom of the bottle trench
150
. Finally, as shown in
FIG. 1
h
, the HSG layer on the protective layer
110
is removed and the HSG layer on the sidewalls and bottom of the bottle trench remains.
In the process described above, overhang is easily caused in the trench due to the sequential formation of ASG layer and TEOS layer in the micro-sized trenches continuously reduced in size. This is not advantageous to the subsequent process for bottle trenches, as process complexity is increased. Consequently, current processes are no longer applicable.
SUMMARY OF THE INVENTION
In order to overcome the above problems, an object of the invention is to provide a method for forming buried plates that avoids the overhang problem and requires fewer steps to form trench capacitors with good performance.
In order to achieve the above objects, there is provided a method for forming buried plates, wherein the formation of ASG layer is omitted and the HSG layer is formed directly after the formation of the bottle trench. A protective layer of TEOS is then formed on the upper portion of the bottle trench, followed by drive-in to form a buried plate. According to the method provided, the number of steps is decreased and overhang problem is avoided.
The method for forming buried plates provided in the present invention comprises providing a substrate formed with a pad stacked layer on the surface, a bottle trench and a protective layer on the upper sidewalls of the bottle trench, forming a doped hemispherical silicon grain (HSG) layer on the protective layer and the sidewalls and bottom of the bottle trench, removing the hemispherical silicon grain layer on the protective layer without removing the hemispherical silicon grain layer on the lower sidewalls and bottom of the bottle trench, forming a covering layer on the protective layer, and subjecting the doped hemispherical silicon grain layer to drive-in annealing so that ions in the HSG layer diffuse out to the substrate, thereby forming a buried plate within the lower sidewalls of the bottle trench.
According to another aspect of the present invention, the method for forming buried plates comprises forming a pad stacked layer on a substrate, defining the pad stacked layer and the substrate to form a deep trench in the substrate; forming a protective layer to cover the pad stacked layer and the upper sidewalls of the deep trench, forming a bottle trench at the lower part of the deep trench; forming a doped hemispherical silicon grain (HSG) layer along the protective layer and the sidewalls of the bottle trench, forming a covering layer on the protective layer, and subjecting the HSG layer to drive-in, thus diffusing the ions doped in the HSG layer to the silicon substrate and forming a buried plate in the sidewalls of the bottle trench.
According to the present invention, the hemispherical silicon grain is preferably doped with dopant such as As. The covering layer is preferably tetraethylorthosilane (TEOS), or silicon nitride (SiN). The protective layer is preferably silicon nitride (SiN) or silicon oxide (SiO
2
). The pad stacked layer comprises a pad oxide layer and a pad nitride layer, sequentially formed by chemical vapor deposition.
In the method for forming buried plates provided in the present invention, the advantages include prevention of overhang and fewer steps, consequently saving production time and costs. As a result, this method helps continuous development of DRAM fabrication at a finer scale, especially for generations less than 0.11 &mgr;m.


REFERENCES:
patent: 5191509 (1993-03-01), Wen

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