Method for forming buried interconnect

Details Method for forming buried interconnect Method for forming buried interconnect

2002-04-12

2004-05-18

Cuneo, Kamand (Department: 2829)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

Reexamination Certificate

active

06737348

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a method for forming a buried interconnect, and more particularly, it relates to a method for forming a buried interconnect employed in fabrication of a semiconductor integrated circuit device, in which a plug is formed in a hole formed in a first insulating film, a second insulating film is deposited on the first insulating film and the buried interconnect is formed in an interconnect groove formed in the second insulating film.
A conventional method for forming a buried interconnect will now be described with reference to
FIGS. 5A through 5D
and
6
A through
6
D.
First, as shown in
FIG. 5A
, a first insulating film
2
of, for example, a silicon oxide film with a thickness of, for example, 600 nm is deposited on a semiconductor or insulating substrate
1
. Thereafter, as shown in
FIG. 5B
, holes
3
each with a diameter of, for example, 250 nm are formed in the first insulating film
2
by known lithography and dry etching.
Next, as shown in
FIG. 5C
, a first underlying film (not shown) composed of a titanium film and a titanium nitride film is deposited over the first insulating film
2
including the inside of the holes
3
, and thereafter, a tungsten film
4
with a thickness of, for example, 200 nm is deposited on the first underlying film by CVD.
Then, the tungsten film
4
and the first underlying film are subjected to first CMP (chemical mechanical polishing), so as to form plugs
5
from the tungsten film
4
as shown in FIG.
5
D.
In the first CMP, slurry including abrasive particles of, for example, silica and an oxidizing agent of, for example, hydrogen peroxide is used. In this case, the CMP is ideally ended when the surface of the first insulating film
2
is exposed, but over-polishing is generally carried out in consideration of variation in the thickness of the tungsten film
4
and variation in the polishing rate. Therefore, as shown in
FIG. 5D
, the first insulating film
2
cannot sufficiently work as a polishing stopper in a region where the plugs
5
are densely formed, and hence, erosion is caused in this region. As a result, a surface level difference A is caused.
Next, as shown in
FIG. 6A
, a second insulating film
6
of, for example, a silicon oxide film with a thickness of, for example, 400 nm is deposited on the first insulating film
2
. Thereafter, as shown in
FIG. 6B
, interconnect grooves
7
are formed in the second insulating film
6
by the known lithography and dry etching.
Then, as shown in
FIG. 6C
, a second underlying film (not shown) composed of a tantalum film and a tantalum nitride film is deposited over the second insulating film
6
including the inside of the interconnect grooves
7
, and thereafter, a copper film
8
is deposited on the second underlying film by, for example, electroplating.
Subsequently, the copper film
8
and the second underlying film are subjected to second CMP, so as to form buried interconnects
9
having a single damascene structure from the copper film
8
as shown in FIG.
6
D.
In the region where the plugs are densely formed, however, since the surface level difference A is caused in the first insulating film
2
due to the erosion caused during the first CMP (as shown in FIG.
5
D), a surface level difference is caused also in the second insulating film
6
(as shown in FIG.
6
A). Therefore, when the buried interconnects
9
are formed by subjecting the copper film
8
to the second CMP, a residual copper film
10
is formed in the region where the plugs are densely formed. As a result, there arises a problem that the buried interconnects
9
are electrically short-circuited through the residual copper film
10
.
Although the formation of the residual copper film
10
can be avoided by carrying out excessive over-polishing in the second CMP, the excessive over-polishing results in lowering the height of the buried interconnects
9
, so that the line resistance of the buried interconnects
9
cannot satisfy required specification. Accordingly, the excessive over-polishing cannot be carried out in the second CMP.
SUMMARY OF THE INVENTION
In consideration of the aforementioned conventional problem, an object of the invention is preventing electric short-circuit between buried interconnects without carrying out excessive over-polishing in CMP performed on a conducting film to be formed into the buried interconnects.
In order to achieve the object, the first method for forming a buried interconnect of this invention comprises the steps of forming holes in a first insulating film deposited on a substrate; depositing a first conducting film over the first insulating film including the holes and subjecting the first conducting film to first CMP, whereby forming plugs from the first conducting film; planarizing the first insulating film by eliminating erosion caused in a region of the first insulating film where the plugs are densely formed through second CMP carried out on the first insulating film with a polishing rate of the first insulating film higher than a polishing rate of the first conducting film; depositing a second insulating film on the first insulating film after planarization and forming interconnect grooves in the second insulating film; and depositing a second conducting film over the second insulating film including the interconnect grooves and subjecting the second conducting film to third CMP, whereby forming buried interconnects from the second conducting film.
In the first method for forming a buried interconnect, the first insulating film is subjected to the second CMP with a polishing rate of the first insulating film higher than that of the first conducting film, so as to planarize the first insulating film by eliminating the erosion caused in the region of the first insulating film where the plugs are densely formed. Thereafter, the second insulating film used for forming the interconnect grooves is deposited on the first insulating film. Therefore, the buried interconnects can be prevented from being short-circuited through a residual copper film without carrying out excessive over-polishing in the third CMP of the second conducting film. Accordingly, it is possible to avoid the problem of line resistance increase of the buried interconnects derived from lowering of the height thereof.
Japanese Laid-Open Patent Publication No. 5-275366 discloses a technique to carry out second CMP on a first insulating film for eliminating a recess (see
FIG. 2
) having been formed in a plug through first CMP. However, this technique is employed for eliminating the recess (generally having a depth of approximately 20 nm) formed in the plug and not for eliminating the erosion (generally having a depth of 30 through 100 nm) formed in the region of the first insulating film where the plugs are densely formed as in this first method. It is noted that erosion is not caused and hence need not be eliminated in a region where the plugs are sparsely formed.
In the first method for forming a buried interconnect, in the case where the first insulating film is a silicon oxide film and the first conducting film is a tungsten film, a thickness of the first insulating film to be polished in the second CMP is preferably 50 nm through 150 nm.
Thus, it is possible to definitely eliminate a surface level difference of generally approximately 30 through 100 nm caused due to the erosion of the region of the first insulating film where the plugs are densely formed.
The second method for forming a buried interconnect of this invention comprises the steps of forming holes in a first insulating film deposited on a substrate; depositing a first conducting film over the first insulating film including the holes and subjecting the first conducting film to first CMP, whereby forming plugs from the first conducting film; depositing a second insulating film on the first insulating film and subjecting the second insulating film to second CMP, whereby planarizing the second insulating film by eliminating a surface level difference caused in the second insulatin

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