Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-03-21
2001-11-13
Wilczewski, Mary (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S299000, C438S655000, C438S592000, C438S595000
Reexamination Certificate
active
06316323
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The proposed invention relates to a method for forming bridge free silicide, and more particularly to a method not only provides a self-aligned contact process in the self-aligned salicide process but also effectively reduces equivalent length of gate by a reverse spacer structure.
2. Description of the Prior Art
Silicide is an important field in contemporary semiconductor fabrication. Advantages of silicide comprise lower contact resistance, withstand high temperature and allowable of self-alignment process. Further, suicides usually are formed by reacting refractory or near noble metals with silicon. Among them are titanium silicide (TiSi2), cobalt silicide (CoSi2), tungsten silicide (Wsi2), platinum silicide (Ptsi2), molybdenum silicide (MoSi2), palladium silicide (PdSi2), and tantalum silicide (TaSi2).
However, owing to the fact that a higher temperature annealing is need to carry out those refractory metal silicide, an unavoidable issue is the bridge phenomena that means the silicide on gate is connected to the silicide on source/drain and then an unexpected short is happened. Sequentially, the bridge phenomena can be further illustrated in following paragraphs.
In conventional salicide process, metal is formed on the gate, the sidewall spacers and the source/drain regions. And then annealing processes are performed to react the metal with the polysilicon (silicon) of the gate and the silicon (polysilicon) of the source/drain to form silicide. Additional, following the first annealing process, all unreacted metal is removed.
Moreover, one of principal functions of sidewall spacers is to separate silicide on the gate from silicide on the source/drain. However, despite the incorporation of spacers, silicide also may form laterally and easily bridge the separation between the gate and the source/drain. Then the gate is shorted to the source/drain, and so-called “bridge phenomena” occurs. In addition, silicon (polysilicon) diffuses into the metal that covers the sidewall spacers and subsequently reacts with the metal.
Further, though silicide can be used to provide self-aligned process and then required precision of photolithography can be decreased. However, the decrement is finite for distance between silicide on gate and silicide on source/drain is finite. Further, in contemporary semiconductor fabrication, spacers are formed on sidewall of gate and then length of gate (critical scale) can not be further reduced to take advantage of silicide to provide excellently self-aligned process.
In summary, it is beyond any doubt that bride phenomena is serious issue in application of silicide, and then a method to take advantage of silicide is instantly required.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide a manufacturable method for preventing the phenomena issue.
Another object of the present invention is to provide a practical silicide scheme that provides a self-aligned contacted process in conventional self-aligned silicide process.
A further object of the present invention is to provide a salicide process that exploits silicide with short equivalent length of gate that is reduced by a reverse spacer structure.
Briefly, first preferred embodiment, a two-step silicide process with a reverse spacer structure, comprises following steps: providing a subs on the polysilicon layer; performing a first rapid thermal process; removing unreacted the first metal layer; filling the trench by a second cap layer; removing the first cap layer and the pad layer that are not located inside the trench region, and then a gate structure is formed; forming a source and a drain inside the substrate; forming a second metal layer on the substrate; performing a second rapid thermal process; removing unreacted the second metal layer; performing a third rapid thermal process; forming a third cap layer on the substrate; and forming a pair of contacts inside the third cap layer.
In comparison, another preferred embodiment is a method for forming transistor with bridge-free silicide and short effective gate length. The method comprises following essential steps: providing a substrate that covered by a first cap layer; forming a trench inside the first cap layer; implanting first ions into the substrate; forming a reverse spacer structure inside the trench; implanting second ions into the substrate; forming a gate structure inside the trench; forming a first silicide layer on the gate structure and then capping the first silicide layer by a second cap layer; removing first cap layer and then forming source/drain; and forming a second silicide layer on source/drain.
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Fang Edberg
Hsieh Wen-Yi
Tsai Teng-Chun
Goodwin David
United Microelectronics Corp.
Wilczewski Mary
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