Method for forming bit line

Details Method for forming bit line Method for forming bit line

2006-05-30

2006-05-30

Smith, Zandra V. (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S618000, C438S672000

Reexamination Certificate

active

07052949

ABSTRACT:
A method for forming a bit line. A semiconductor substrate is provided. A MOS having a gate and an S/D area is formed on the semiconductor substrate. A first dielectric layer with a first opening is formed on the semiconductor substrate to expose the S/D area. A conducting layer is formed in the first opening. A barrier layer is formed on the surface of the first dielectric layer and the conducting layer. A second dielectric layer having a second opening and a third opening is formed on the barrier layer, the position of the second opening corresponding to the first opening. Metal layers are formed in the second opening and the third opening as bit lines, respectively.

REFERENCES:
patent: 5817572 (1998-10-01), Chiang et al.
patent: 5956594 (1999-09-01), Yang et al.
patent: 6093628 (2000-07-01), Lim et al.
patent: 6100135 (2000-08-01), Wu
patent: 6133083 (2000-10-01), Lin et al.
patent: 6342416 (2002-01-01), Kim et al.
patent: 6525357 (2003-02-01), Amano et al.
patent: 6611449 (2003-08-01), Hilliger
patent: 2002/0076895 (2002-06-01), Chien et al.

Affiliated with

Also associated with

Rating

Method for forming bit line does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for forming bit line, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming bit line will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3651806