Method for forming asymmetric flash EEPROM with a pocket to focu

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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438266, 438286, 438525, H01L 21336

Patent

active

061301345

ABSTRACT:
A memory cell having an asymmetric source and drain connection to virtual ground bit-lines. A main diffusion, adjacent the drain and displaced from the source, allows Fowler-Nordheim (FN) tunneling erasure on the drain side of the floating gate. A pocket diffusion, between the main diffusion and the source, concentrates the electric field and thereby enhances the efficiency of programming by electron injection on the source side of the floating gate. A nonvolatile semiconductor memory device comprising row and column arrangement of the cells, in which adjacent columns of cells share a single virtual ground bit line. The method for manufacturing a memory cell having asymmetric source and drain regions and comprising the steps of: (1) forming a semiconductor substrate having a first conductivity type; (2) forming a dielectric covering a semiconductor substrate; (3) forming a first and second column of floating gates on the dielectric; (4) implanting a first dopant along a first dopant strip, the first dopant strip aligned adjacent the first column and displaced from the second column and having a second conductivity type opposite the first conductivity type; (5) implanting a second dopant in a second dopant strip, aligned with the first dopant strip and extending below the second column, the second dopant having an enhancement of the first conductivity type; and (6) completing formation of control gate dielectric and control gates. The manufacturing method of the present invention results in a cell, which increases floating gate memory array density and programming speed while reducing power consumption and the likelihood of a disturb condition.

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