Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-11-21
2001-09-25
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S258000, C438S427000
Reexamination Certificate
active
06294423
ABSTRACT:
BACKGROUND
1. Technical Field
This disclosure relates to semiconductor fabrication, and more particularly, to a method for forming and filling trenches of different sizes in a single process.
2. Description of the Related Art
Shallow trench isolations (STI) structures are provided in semiconductor chips to isolate integrated semiconductor devices, such as, transistors. STI structures are formed in trenches etched from a silicon substrate or other materials adjacent to an active area of a semiconductor chip layout. These trenches are typically etched down to a depth of about 250 nm to 300 nm. These trenches are usually lined with a nitride liner and/or a thermally grown oxide liner and filled with an oxide material to provide isolation between semiconductor devices.
In certain situations, STI regions are required at greater depths. In these cases, aggressive filling of the trenches may cause voids or an incomplete fill. This can have consequences on chip yield and on device reliability. Therefore, very restrictive gapfill requirements are needed in order to ensure a complete fill. Further, since all trenches may not be of a same depth or same opening width, different processes may be needed to fill the different trenches.
Therefore, a need exists for a method of defining a depth for trench isolation structures which maintains an aspect ratio of the trenches to permit a complete fill.
SUMMARY OF THE INVENTION
A method for forming isolation trenches forms, in a substrate, a plurality of trenches having different widths including widths above a threshold size and widths below a threshold size. The plurality of trenches have a same first depth.
A masking layer is deposited in the plurality of trenches, the masking layer has a thickness sufficient to both line the trenches with the widths above the threshold size and completely fill the trenches with the widths below the threshold size. A portion of the substrate is exposed at the bottom of the trenches with the widths above the threshold size by etching the masking layer. The plurality of trenches is etched to extend the trenches with the widths above the threshold size to a different depth.
Another method for forming isolation trenches in semiconductor devices, includes the steps of forming, in a substrate, first trenches having a first width and second trenches having a second width wherein the first width is larger than the second width and the first and second trenches have a same first depth, depositing a masking layer in the first and second trenches, the masking layer including a thickness sufficient to both line the first trenches and completely fill the second trenches, exposing a portion of the substrate at a bottom of the first trenches by etching the masking layer to form an opening through the masking layer at the first depth, and etching the first and second trenches to extend the first trenches to a second depth.
Yet another method for forming isolation trenches in semiconductor devices includes the steps of providing a semiconductor substrate having a memory array area and a support area formed thereon, forming, in the semiconductor substrate, first trenches having a first width in the memory array area and second trenches having a second width in the support area, wherein the first width is larger than the second width and the first and second trenches have a same first depth, depositing a masking layer in the first and second trenches, the masking layer including a thickness sufficient to both line the first trenches and completely fill the second trenches, exposing a portion of the substrate at a bottom of the first trenches by etching the masking layer to form an opening through the masking layer at the first depth, etching the first and second trenches to extend the first trenches to a second depth while maintaining an aspect ratio of the first trenches below a threshold value and filling the first trenches to the second depth and the second trenches to the first depth with a dielectric material in a single deposition step.
In other methods, the step of forming, in a substrate, a plurality of trenches may include the steps of forming the trenches with the widths above the threshold size in a memory array and forming the trenches with the widths below the threshold size in a support area. The step of depositing a masking layer may include the step of conformally depositing the masking layer with a low pressure chemical vapor deposition process. The masking layer may include TEOS. The method may include the step of maintaining an aspect ratio of the different depths below a value for the trenches with the widths above the threshold size. The method may include the step of filling the plurality of trenches in a single deposition step. The aspect ratio is preferably less than or equal to 5. The step of etching the plurality of trenches may include the step of anisotropically etching the trenches to increase the depth of the trenches with the widths above the threshold size. The step of etching the plurality of trenches may include the step of isotropically etching the trenches to increase the width of the trenches with the widths above the threshold size.
These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.
REFERENCES:
patent: 4495025 (1985-01-01), Haskell
patent: 5384280 (1995-01-01), Aoki et al.
patent: 5536675 (1996-07-01), Bohr
patent: 5731221 (1998-03-01), Kwon
patent: 5804490 (1998-09-01), Fiegl et al.
patent: 5851899 (1998-12-01), Weigand
patent: 5895253 (1999-04-01), Akram
patent: 5950093 (1999-09-01), Wei
patent: 5981357 (1999-11-01), Hause et al.
patent: 6133083 (2000-10-01), Lin et al.
Knorr Andreas
Malik Rajeev
Seitz Mihel
Booth Richard
Braden Stanton C.
Infineon Technologies North America Corp.
Kennedy Jennifer M.
LandOfFree
Method for forming and filling isolation trenches does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for forming and filling isolation trenches, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming and filling isolation trenches will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2539169