Method for forming an oxide layer on a nitride layer

Details Method for forming an oxide layer on a nitride layer Method for forming an oxide layer on a nitride layer

2002-03-21

2003-04-22

Booth, Richard (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S763000, C438S766000, C438S981000

Reexamination Certificate

active

06551879

ABSTRACT:

FIELD OF THE INVENTION
This invention relates in general to a semiconductor manufacturing process and, more particularly, to a manufacturing process for forming an oxide layer on a nitride layer.
BACKGROUND OF THE INVENTION
In a flash memory device, there are generally two types of transistors formed on the device substrate. The first transistor type is a flash memory cell for storing data. The flash memory device includes a memory array having a plurality of flash memory cells formed contiguous with one another. The memory array is sometimes referred to as the “core” of the flash memory device. A second transistor type is the conventional metal-oxide-silicon (“MOS”) transistor used in various circuits, such as sense amplifiers and charge pumps, of the flash memory device. MOS transistors are generally located around the flash memory array, or on the “peripheral” of the device substrate.
A flash memory cell and a traditional MOS transistor differ structurally in that the flash memory cell includes an additional polysilicon gate, termed “floating gate,” positioned between the device substrate and a second polysilicon gate. The second polysilicon gate is the “control gate” of the flash memory cell. The control gate of the flash memory cell is separated from the floating gate by an oxide-nitride-oxide (“ONO”) layer. The ONO layer includes a first oxide layer grown through a high temperature process over the floating gate. A nitride layer is then deposited over the first oxide layer, and a second oxide layer is grown over the nitride layer. For the MOS transistor, there does not include a floating gate and the “second polysilicon gate” is the traditional gate structure. Even though the MOS transistors and flash memory cells are different structurally, they are formed near contemporaneously in the manufacturing process of the flash memory device.
During the manufacturing process, the thickness of the top layer of the ONO layer, i.e., the second oxide layer, is difficult to control as a portion of the second oxide layer may be unintentionally etched away by certain chemical solutions used in the subsequent manufacturing steps, such as during the definition of the core area and etching of the periphery area, each of which uses a hydrogen-fluoride (HF) solution. It is known that oxide layers are susceptible to etching by the HF solution. One prior art manufacturing process attempts to address this problem by growing a thicker second oxide layer during its formation to account for the anticipated layer loss in the subsequent manufacturing steps. However, it is known in the art that growing an oxide layer on a nitride layer is difficult and time-consuming. The prior art manufacturing process, therefore, expends additional time, energy, and resources to increase the thickness of the second oxide layer. In addition, if the second oxide layer is not etched in the manner or at a rate as anticipated during the subsequent manufacturing step, the ONO layer would have a larger-than-expected thickness. As a result, certain portions of the ONO layer may not be completely removed as required by the design specification during the formation of the control gate, creating an ONO “fence” that impedes the subsequent manufacturing steps.
SUMMARY OF THE INVENTION
In accordance with the invention, there is provided a method for forming a semiconductor device that includes defining a substrate to include a peripheral section and a core section, masking the peripheral section of the substrate, growing a first dielectric layer over the core section of the substrate, depositing a first polysilicon layer over the first dielectric layer for forming at least one gate structure, growing a first oxide layer over the first polysilicon layer, depositing a nitride layer over the first oxide layer, implanting oxygen ions into the nitride layer, unmasking the peripheral section of the substrate, and growing a second oxide layer over the nitride layer, wherein the growth rate of the second oxide layer is increased due to the implantation of oxygen ions in the nitride layer.
In one aspect, the method also includes a step of cleaning the nitride layer after the step of oxygen ion implantation.
In another aspect, the method further includes a step of growing a gate oxide in the peripheral section of the substrate contemporaneously with the step of growing a second oxide layer.
Also in accordance with the present invention, there is provided a method for forming a semiconductor device that includes defining a substrate, growing a first dielectric layer over the core section of the substrate, depositing a first polysilicon layer over the first dielectric layer for forming at least one gate structure, growing a first oxide layer over the first polysilicon layer, depositing a nitride layer over the first oxide layer, implanting oxygen ions into the nitride layer, and growing a second oxide layer over the nitride layer, wherein the growth rate of the second oxide layer is increased due to the implantation of oxygen ions in the nitride layer.
Additional objects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.


REFERENCES:
patent: 6103576 (2000-08-01), Deustcher et al.
patent: 6184093 (2001-02-01), Sung
patent: 6248630 (2001-06-01), Clementi et al.
patent: 6265267 (2001-07-01), Huang

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