Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-08-11
1999-09-28
Niebling, John F.
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438585, 438586, 438595, 438596, H01L 21336
Patent
active
059602708
ABSTRACT:
A method for forming a metal gate MOS transistor begins by forming source and drain electrodes (26, 28, and/or 118) within a substrate (12 or 102). These source and drain regions (26, 28, and 118) are self-aligned to a lithographically-patterned feature (24 or 108). After formation of the source and drain regions, the features (24 and 108 are processed to fill these features with a metallic gate layer (28a or 128a). This metal layer (28a or 128a) is then chemically mechanically polished (CMPed) to form a metallic plug region (28b or 128b) within the features (24 or 108). The plug region (28b or 128b) is formed in either an inlaid or dual inlaid manner wherein this metallic plug region (28b or 128b) is self-aligned to the previously formed source and drain regions and preferably functions as a metal MOS gate region.
REFERENCES:
patent: 5391510 (1995-02-01), Hsu et al.
patent: 5393681 (1995-02-01), Witek et al.
patent: 5434093 (1995-07-01), Chau et al.
patent: 5447874 (1995-09-01), Grivna et al.
patent: 5716861 (1998-02-01), Moslehi
Cope Jeffrey S.
Hobbs Christopher C.
Misra Veena
Smith Brad
Venkatesan Suresh
Gurley Lynne A.
Motorola Inc.
Niebling John F.
Witek Keith E.
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