Method for forming an MIM capacitor

Details Method for forming an MIM capacitor Method for forming an MIM capacitor

2003-07-23

2004-11-16

Blum, David S. (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S396000

Reexamination Certificate

active

06818499

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method for forming a metal-insulator-metal (“MIM”) capacitor; and, more particularly, to a method for forming an MIM capacitor capable of preventing an undesired etching of a lower metal film and an occurrence of a bridge between electrodes due to a re-deposition of an etched metal film.
BACKGROUND OF THE INVENTION
An analog capacitor typically has an MIM structure instead of a polysilicon-insulator-polysilicon (“PIP”) structure. This is because a capacitor used for an analog circuit in RF band requires a high quality factor; and, in order to obtain such capacitor, a metal electrode having no depletion and low resistance should be used as an electrode material therefor.
A conventional method for forming an MIM capacitor will now be described with reference to
FIGS. 1A
to
1
C.
Referring to
FIG. 1A
, a semiconductor substrate
1
with an underlying layer (not shown) is prepared; and a first metal film
2
, a insulation film
3
and a second metal film
4
are sequentially formed on the substrate
1
.
Referring to
FIG. 1B
, a mask pattern (not shown) is provided on the second metal film
4
by using a known process, and the second metal film
4
and the insulation film
3
are in turn etched by using the mask pattern, thereby forming an upper electrode
4
a
of the MIM capacitor over the first metal film
2
.
Referring to
FIG. 1C
, with the mask pattern removed, the first metal film
2
is patterned in accordance with a known photolithography process to form a lower electrode
2
a
of the MIM capacitor, thereby resulting in the MIM capacitor
10
.
In the conventional MIM capacitor forming process, the metal film for the upper electrode and the insulation film are simultaneously etched and the insulation film is over-etched for a complete etching thereof. In this procedure, as shown in
FIG. 1B
, the surface of the metal film for the lower electrode may be etched and then re-deposited, thereby producing a bridge between the upper and the lower electrode. Accordingly, the reliability and the yield of the MIM capacitor are deteriorated.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a method for forming an MIM or PIP capacitor which is capable of preventing an undesired etching of a lower film and an occurrence of a bridge between electrodes due to re-deposition of an etched film.
In accordance with an aspect of the present invention, there is provided a method for forming a metal-insulator-metal (“MIM”) capacitor comprising the steps of: forming a first metal film and an dielectric film on a semiconductor substrate; patterning the dielectric film to form a trench through which the first metal film is exposed; sequentially forming a insulation film and a second metal film on a surface of the trench and the dielectric film; providing a mask pattern defining a capacitor forming area on the second metal film; forming an upper electrode by etching the second metal film and the insulation film by using the mask pattern and the dielectric film as an etching barrier and an etching stopper layer, respectively; removing the mask pattern; and forming a lower electrode by patterning the dielectric film and the first metal film.
In accordance with another aspect of the present invention, there is provided a method for forming a polysilicon-insulator-ploysilicon (“PIP”) capacitor comprising the steps of:
forming a first polysilicon film and an dielectric film on a semiconductor substrate;
patterning the dielectric film to form a trench through which the first polysilicon film is exposed;
forming an insulation film and a second polysilicon film on a surface of the trench and the dielectric film;
providing a mask pattern defining a capacitor forming area on the second polysilicon film;
forming an upper electrode by etching the second polysilicon film and the insulation film by using the mask pattern and the dielectric film as an etching barrier and an etching stopper layer, respectively;
removing the mask pattern; and
forming a lower electrode by patterning the dielectric film and the first polysilicon film.


REFERENCES:
patent: 6144051 (2000-11-01), Nishimura et al.
patent: 6333224 (2001-12-01), Lee
patent: 6479850 (2002-11-01), Lee
patent: 6569746 (2003-05-01), Lee et al.
patent: 6597032 (2003-07-01), Lee

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