Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Multiple layers
Reexamination Certificate
1999-11-19
2001-09-25
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Multiple layers
C438S696000, C438S723000, C438S763000, C438S787000
Reexamination Certificate
active
06294480
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of the Invention
This invention relates generally to fabrication of a semiconductor device and more particularly to a method for forming an L-shaped spacer using a sacrificial organic top coating.
2. Description of the Prior Art
As the physical geometry of semiconductors continues to shrink, the space between gate electrodes shrinks as well. The reduced space between gate electrodes can cause poor gap fill by the subsequent dielectric layer (eg inter-layer dielectric) resulting in degraded performance.
One approach which has been used to solve this problem is the use of spacers on the gate electrode sidewalls which are smaller at the top than they are at the bottom, such as L-shaped spacers. In a typical L-shaped spacer two dielectric layers (the first composed of silicon nitride and the second composed of silicon oxide) are formed over and around a gate electrode, then anisotropically etched. However, the top oxide portion of the spacer can not be easily removed without damaging oxide isolation structures. Conversely, if the top oxide portion of the spacer remains, it can be effected by post-etch wet chemical process causing inconsistent spacer shape and size across the IC and between IC's. Also, the gap filling ability of the subsequent dielectric layer is not optimized, because the aspect ratio remains high due to the presence of the oxide portion of the spacers.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following patents.
U.S. Pat. No. 4,838,991 (Cote et al.) recites a process for defining organic sidewall structures on a photoresist pattern to enhance a photolithography process.
U.S. Pat. No. 5,858,847 (Zhou et al.) shows a LDD process using a photoresist block over a hard mask and surrounded by a polymer layer to provide a highly-doped source and drain implant mask, then removing the polymer layer and photoresist block for the lightly-doped source and drain implant.
U.S. Pat. No. 4,868,617 (Chiao et al.) and U.S. Pat. No. 5,024,959 (fiester) show L-shaped spacers and processes.
U.S. Pat. No. 5,882,973 (Gardner et al.) shows double spacers used to increase the length of source and drain extensions for particular transistors in an IC.
U.S. Pat. No. 5,234,852 (Liou) shows sloped spacers formed using a reflowable material.
U.S. Pat. No. 5,770,508 (Yeh et al.) shows a process for forming an L-shaped spacer using an oxide layer and an overlying nitride layer, anisotropically etching to form spacers, then removing the nitride layer, leaving an L-shaped oxide spacer. Ions are implanted through the L-shaped spacer to form shallow source and drain extensions under the L-shaped spacer and moderate depth source and drain regions beyond the L-shaped spacer.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for forming an L-shaped spacer using an organic top coating.
It is another object of the present invention to provide a method for forming an L-shaped spacer that has a reduced susceptibility to post-etch wet chemical processing.
It is another object of the present invention to provide a method for forming an L-shaped spacer that provides for better gap filling properties of the subsequently formed, overlying dielectric layer.
It is yet another object of the present invention to provide a method for forming an L-shaped dielectric spacer with a reduced cycle time and a reduced thermal budget.
To accomplish the above objectives, the present invention provides a method for forming an L-shaped spacer using a sacrificial organic top coating. A semiconductor structure is provided having a gate structure thereon. A liner oxide layer is formed on the gate structure. A dielectric spacer layer is formed on the liner oxide layer. In the preferred embodiment, the dielectric spacer layer comprises a silicon nitride layer or a silicon oxynitride layer. A sacrificial organic layer is formed on the dielectric spacer layer. The sacrificial organic layer and the dielectric spacer layer are anisotropically etched to form spacers comprising a triangle-shaped sacrificial organic structure and an L-shaped dielectric spacer. The liner oxide layer can act as an etch stop for the anisotropic etch process. The triangle-shaped sacrificial organic structure is removed using an etch selective to the L-shaped dielectric spacer, leaving an L-shaped dielectric spacer which is sufficiently open to provide for good gap filling properties of the overlying dielectric layer.
The present invention provides considerable improvement over the prior art. The sacrificial organic layer can be deposited in less time than an oxide layer, as is used in the prior art, reducing cycle time. The organic dielectric layer also requires a lower thermal budget to form than does an oxide layer. The spacer which results from the process of the present invention is less susceptible to post-etch wet chemical processing than an oxide layer, resulting in a more uniform spacers, both across the IC and between IC's. Because the sacrificial organic structure can be completely removed using a selective etch, the resulting L-shaped dielectric spacers are open and provide better gap filling properties of the subsequent dielectric layer (eg interlevel dielectric).
The present invention achieves these benefits in the context of known process technology. However, a further understanding of the nature and advantages of the present invention may be realized by reference to the latter portions of the specification and attached drawings.
REFERENCES:
patent: 4838991 (1989-06-01), Cote et al.
patent: 4868617 (1989-09-01), Chiao et al.
patent: 5024959 (1991-06-01), Pfiester
patent: 5069747 (1991-12-01), Cathey et al.
patent: 5234852 (1993-08-01), Liou
patent: 5290720 (1994-03-01), Chen
patent: 5397733 (1995-03-01), Jang
patent: 5714413 (1998-02-01), Brigham et al.
patent: 5770508 (1998-06-01), Yeh et al.
patent: 5858847 (1999-01-01), Zhou et al.
patent: 5882973 (1999-03-01), Gardner et al.
patent: 5897349 (1999-04-01), Agnello
patent: 6156598 (2000-12-01), Zhou et al.
Fan Minghui
Pradeep Yelehanka Ramachandramurthy
Yap Chiew Wah
Yu Jie
Chartered Semiconductor Manufacturing Ltd.
Chaudhari Chandra
Pike Rosemary L. S.
Saile George O.
Sarkar Asok Kumar
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