Method for forming an inter-layer dielectric layer

Details Method for forming an inter-layer dielectric layer Method for forming an inter-layer dielectric layer

1999-09-09

2001-08-28

Utech, Benjamin L. (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S719000, C438S723000, C438S743000

Reexamination Certificate

active

06281133

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a method for forming an inter-layer dielectric layer, and more particularly, to a method for forming a second inter-poly dielectric layer.
2. Description of the Related Art
In a integrated circuit having a high integration, in addition to a first polysilicon layer used as word lines, there is at least a second polysilicon layer to form a functional structure such as bit lines or capacitors. When the second polysilicon layer is formed, an inter-poly dielectric (IPD) layer is then formed thereon to isolate from an upper device such as an interconnect or a third polysilicon layer. However, due to the second polysilicon layer having a greater thickness (especially when a capacitor is formed), a planarization process and an etching back process are normally performed to form a planarized second polysilicon layer.
FIG.
1
A through
FIG. 1C
are schematic, cross-sectional views showing a conventional process for forming a second inter-poly dielectric layer according to the prior art.
Referring to
FIG. 1A
, a substrate
100
is provided, and then a first polysilicon layer
102
, a first inter-layer dielectric layer
104
and a second polysilicon layer
106
are formed on the substrate
100
. Then, a second IPD layer
108
is formed on the resulting structure. Due to the difference in height between the second polysilicon layer
106
and the first inter-layer dielectric layer
104
, the second IPD layer
108
as formed has an undulating surface, as shown in FIG.
1
A. Thus, a spin-on glass (SOG) layer
110
is further formed thereon to generate a uniform surface.
Referring to
FIG. 1B
, the SOG layer
110
and the second IPD layer
108
are etched back to entirely remove the SOG layer
110
and partially remove the second IPD layer
108
; thus, the surface of the second IPD layer
108
is planarized.
Referring to
FIG. 1C
, a silicon nitride layer
114
and an oxide layer
116
are formed on the planarized second IPD layer
108
in sequence; thus, an inter-layer dielectric layer is completed. The distance from a top surface of the second polysilicon layer
106
to a top surface of the planarized second IPD layer
108
is denoted as a reference numeral
112
.
However, according to the prior art, in the step of etching the SOG layer
110
and the second IPD layer
108
back, a time mode is adopted; that is, the processing time of etching is predetermined. Thus, once the schedule is completed, the etching is terminated.
The time mode is readily influenced by deviation in deposited thickness and improper control in etching rate. Thus, the desired thickness of the dielectric layer etched cannot be properly provided. Therefore, conventionally, the present method to prevent excessive etching is to deposit an assured thickness (the reference number
112
in
FIG. 1B
) in order to prevent the second IPD layer
108
from being lower than the surface of the second polysilicon layer
106
due to deviation in process. However, the assured thickness on the second polysilicon layer
106
increases difficulty in subsequently etching the dielectric layer because the etching depth is increased.
SUMMARY OF THE INVENTION
The invention provides an effective method of controlling the thickness of the second IPD layer. The method can prevent the second IPD layer from being lower than the second polysilicon layer due to deviation in process. In addition, increasing the thickness of the second IPD layer is not required; thus, the etching depth does not increase.
As described above, a method for forming an inter-layer dielectric layer is provided. A substrate is provided. Sequentially, first polysilicon lines, a first inter-layer dielectric layer, and a plurality of second polysilicon lines are formed on the substrate. A second inter-layer dielectric layer is formed between the second polysilicon lines and covers the second polysilicon lines. A spin-on glass layer is formed on the second inter-layer dielectric layer. Using upper surfaces of the second polysilicon lines as etch end points, the spin-on glass layer and the second inter-layer dielectric layer are etched back to entirely remove the spin-on glass layer and partially remove the second inter-layer dielectric layer over the second polysilicon lines. Subsequently, a cover layer is formed to cover the second polysilicon lines and the remainder of the inter-layer dielectric layer. An oxide layer is formed to cover the resulting structure.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5399533 (1995-03-01), Pramanik et al.
patent: 5552346 (1996-09-01), Huang et al.
patent: 5665657 (1997-09-01), Lee
patent: 6057603 (2000-05-01), Dawson

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