Method for forming an integrated circuit interconnect using...

Details Method for forming an integrated circuit interconnect using... Method for forming an integrated circuit interconnect using...

1995-02-17

2004-05-25

Quach, T. N. (Department: 2814)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S633000, C438S647000, C438S672000

Reexamination Certificate

active

06740573

ABSTRACT:

FIELD OF THE INVENTION
The invention is related to fabrication of a semiconductor, and more particularly to the fabrication of a polycrystalline silicon interconnect.
BACKGROUND ART
In some semiconductor buried contact applications upper
1
and lower
2
polycrystalline silicon layers form an electrical interconnect
3
to a substrate, see FIG.
1
A. In the process for forming the electrical interconnect
3
polycrystalline silicon layer
1
is masked to define the electrical interconnect
3
. Polysilicon
1
, overlying polycrystalline silicon
2
, and polycrystalline silicon
2
are etched to form the interconnect according to the mask. Typically a defect can occur along the horizontal interface between the upper
1
and lower
2
polycrystalline silicon layers. In one case the defect degrades the integrity of the electrical contact by preventing etching of the lower polycrystalline silicon layer in areas which are exposed during etching. This polycrystalline silicon which is not etched when intended can bridge between two poly interconnects thereby causing malfunctions in the part.
In one solution a single poly process is used, see FIG.
1
B. In the single poly process a single layer of polycrystalline silicon is deposited and masked to form an electrical interconnect
4
. However contamination problems occur at the poly/oxide interface during buried contact formation when the single poly process is used. In addition a required hydrofluoric acid etch thins the gate oxide layer creating a non uniform gate oxide.
In addition when patterning a polycrystalline silicon above a buried contact region, trenching of the substrate and exposure of the buried contact region often occur due to misalignment. Thus a need exists to protect the buried contact from exposure and trenching during gate patterning. In one solution a buried contact cap is used to protect the buried contact region. However a parasitic transistor is formed around the contact cap thereby degrading the performance of the device. In one solution an implant mask has been added to lower contact resistance and eliminate parasitic transistor problems.
Thus a need exits for a method having minimal contamination when forming a polycrystalline silicon interconnect which has integrity within the contact without reflective notching. The method must also retain a conformal gate oxide layer without trenching or exposing the substrate.
SUMMARY OF THE INVENTION
The invention is a method for forming an electrical interconnect, typically of polycrystalline silicon (although amorphous silicon or other electrically conductive materials may be used), overlying a buried contact region of a substrate. A first electrically conductive layer, typically of polycrystalline silicon (poly
1
), is deposited to overlie the substrate. The poly
1
is patterned and etched to form a via thereby exposing the substrate. A second electrically conductive layer, typically of polycrystalline silicon (poly
2
), is deposited to overlie the substrate and the poly
1
layer. In a first embodiment the poly
2
layer is chemically mechanically planarized to remove the poly
2
layer overlying the poly
1
layer thereby eliminating a horizontal interface between the poly
1
and the poly
2
layers.
In a second embodiment a layer resistant to a polycrystalline silicon etch is created prior to the patterning and etch of the poly
1
layer and prior to the deposition of the poly
2
layer. This layer will be referred to as a first polycrystalline silicon etch stop layer or just first etch stop layer. The first etch stop layer is patterned and etched to expose the poly
1
in the buried contact region. The poly
1
layer is then etched to expose the buried contact region of the substrate and poly
2
is deposited to overlie the remaining first etch stop layer and buried contact region. The poly
2
is then removed to expose the etch stop layer. Poly
2
remains in the via.
At this juncture a layer which is capable of reacting with silicon to form a silicon etch stop layer is deposited to overlie the first etch stop layer and the second polycrystalline silicon layer. A reaction is created between the second polycrystalline silicon layer and the layer which is capable of reacting with silicon, typically titanium. A second etch stop layer, resistant to a polycrystalline silicon etch, is formed overlying the poly
2
layer as a result of the reaction. The first etch stop layer functions as a protective layer during the reaction to prohibit a reaction between the poly
1
layer and the layer which is capable of reacting with silicon. The second etch stop layer eliminates trenching and exposure of the substrate even with gross misalignment of the photoresist mask during an etch of the poly
1
to form the interconnect.
In a further embodiment the invention is a semiconductor interconnect for electrically connecting a first region of a substrate and a second region of the substrate. The semiconductor interconnect comprises an electrically conductive silicon plug overlying and in electrical contact with the first region and the second region and an electrically conductive silicon layer, without a silicon interface horizontal to the substrate. The electrically conductive silicon layer is electrically isolated from the substrate and interposed between the silicon plug overlying the first region and the silicon plug overlying the second region. The interface between the silicon plug overlying the first region and the silicon layer is vertical to the substrate as is the interface between the silicon plug overlying the second region and the silicon layer.


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