Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-01-27
1999-03-16
Tsai, Jey
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438286, 438303, H01L 21336
Patent
active
058829733
ABSTRACT:
An integrated circuit is provided having a plurality of transistors either NMOS transistors, or PMOS transistors, or both NMOS and PMOS transistors. The transistors are formed having dissimilarly sized spacers. The spacers can be made larger in lateral areas on transistors designated as lower performing transistors than smaller spacers used on transistors which are higher performing. The dissimilarly sized spacers produce correspondingly sized lightly doped drain (LDD) areas. Accordingly, the present integrated circuit includes on a single monolithic substrate both high and low performance transistors based upon formation of dissimilarly sized spacers at sidewall surfaces of select transistor gate conductors.
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Fulford, Jr. H. Jim.
Gardner Mark I.
Hause Fred N.
Advanced Micro Devices , Inc.
Daffer Kevin L.
Tsai Jey
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