Method for forming an integrated circuit

Details Method for forming an integrated circuit Method for forming an integrated circuit

1998-01-30

2000-10-17

Niebling, John F.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

H01L 21336

Patent

active

061330930

ABSTRACT:
In one embodiment, the reliability of an integrated circuit having a floating gate device (50), a high breakdown voltage transistor (52), and a low breakdown voltage transistor (54), which are electrically isolated from each other by a trench isolation region (12), is improved by using an oxidation resistant layer (24). The oxidation resistant layer (24) protects portions of the trench isolation region (12) when the gate dielectric layer (30) for the high breakdown voltage transistor (52) is formed, and when the gate dielectric layer (36) for the low breakdown voltage transistor (54) is formed. The oxidation resistant layer (24) minimizes etching of the field isolation region (12) so that thinning or recessing of the field isolation region (12) is minimized.

REFERENCES:
patent: 4420871 (1983-12-01), Scheibe
patent: 5116775 (1992-05-01), Katto et al.
patent: 5278087 (1994-01-01), Jenq
patent: 5587332 (1996-12-01), Chang et al.
patent: 5830795 (1998-11-01), Metha et al.
patent: 5861347 (1999-01-01), Maiti et al.

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