Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-09-06
2002-05-14
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S183000, C438S286000, C438S303000, C438S588000, C438S595000
Reexamination Certificate
active
06387765
ABSTRACT:
BACKGROUND OF INVENTION
1) Field of the Invention
This invention relates generally to fabrication of a semiconductor device and more particularly to a method for forming a self-aligned, extended metal gate using a damascene process.
2) Description of the Prior Art
As semiconductor geometries continue to shrink, and design requirements demand faster performance, gate contact resistance becomes increasingly important to reduce the circuit delay. Metal gates are an attractive option for reducing gate contact resistance, however, several problems prevent economical commercial manufacturing of metal gates.
Etching the top layer of a gate structure to expose form an opening for a metal gate layer can cause erosion of the adjacent dielectric material (eg. gapfill layer or STI). This erosion of the gapfill layer can cause poly wrap around effects wherein a higher electrical field is created where a polysilicon layer fills in the gap caused by the erosion, increasing the risk of poly breakdown.
Another problem associated with forming metal gates as gate geometries continue to shrink is that patterning accuracy is reduced by performing photolithography on non-planar surfaces. Because prior art processes for forming metal gates require to photolithography steps to be performed on non-planar surfaces, the necessary patterning accuracy is difficult to achieve.
Also, as gate geometries continue to shrink, it becomes difficult to land contacts on the gate structure. To compensate for this, dogbone structures that extend over field isolation structures are formed to provide increase area for landing contacts. However these dogbone structures increase contact resistance causing circuit delay.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following patents.
U.S. Pat. No. 5,422,289 (Pierce) shows a planarized source and drain and gate contact structure.
U.S. Pat. No. 5,856,227 (Yu et al.) shows a polycide gate process formed by ion implant through a thin residual polysilicon layer, followed by oxidation of the thin residual polysilicon layer.
U.S. Pat. No. 5,915,183 (Gambino et al.) shows a raised source and drain contact using recessed etch of a blanket polysilicon layer.
U.S. Pat. No. 5,807,779 (Liaw) shows a process for forming self-aligned source and drain contacts and local interconnect structures.
U.S. Pat. No. 5,869,396 (Pan et al.) shows a method for forming a polycide gate contact.
U.S. Pat. No. 5,856,225 (Lee et al.) shows a process for forming an implanted channel region by removing a dummy gate to form an implant opening and forming a self-aligned gate in the opening.
U.S. Pat. No. 5,731,239 (Wong et al.) shows a method for forming self-aligned silicide gate electrodes.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for forming an self-aligned, extended metal gate using a damascene process.
It is another object of the present invention to provide an integrated method for forming a self-aligned, extended metal gate and self-aligned metal source and drain contacts with a single mask and etching step.
It is another object of the present invention to provide a method for eliminating the poly wrap-around effect at the STI/source and drain junction.
It is yet another object of the present invention to provide a method for forming an extended self-aligned gate with reduced topography variation during photolithography.
To accomplish the above objectives, the present invention provides a method for forming an extended metal gate without poly wrap around effects. The method begins by providing a semiconductor structure having a gate structure thereon. The gate structure comprising a gate dielectric layer, a gate silicon layer, a doped silicon oxide layer, and a disposable gate layer stacked sequentially. Spacers are formed on the sidewalls of the gate structure. A dielectric gapfill layer is formed over the semiconductor structure and the gate structure and planarized, stopping on the disposable gate layer. A first silicon nitride layer is formed over the disposable gate layer, and a dielectric layer is formed over the first silicon nitride layer. The dielectric layer is patterned to form a trench over the gate structure; wherein the trench has a width greater than the width of the gate structure. The first silicon nitride layer in the bottom of the trench and the disposable gate layer are removed using one or more selective etching processes. The doped silicon oxide layer is removed using an etch with a high selectivity of doped silicon oxide to undoped silicon oxide. A barrier layer is formed over the gate silicon layer, and a metal gate layer is formed on the barrier layer; whereby the metal gate layer has a greater width than the gate structure.
The present invention provides considerable improvement over the prior art. Extended metal gates allow for increased tolerance for landing gate contacts, eliminating the need for dogbone structures over the field isolation structures. Because the present invention provides high selectivity of the doped silicon layer in the gate structure to the undoped silicon of the gapfill layer, poly wrap around effects can be avoided. Also, since each photolithography step is performed on a planar topography, the photolithography process error can be reduced, increasing the patterning accuracy.
The present invention achieves these benefits in the context of known process technology. However, a further understanding of the nature and advantages of the present invention may be realized by reference to the latter portions of the specification and attached drawings.
REFERENCES:
patent: 5422289 (1995-06-01), Pierce
patent: 5539229 (1996-07-01), Noble, Jr. et al.
patent: 5731239 (1998-03-01), Wong et al.
patent: 5807779 (1998-09-01), Liaw
patent: 5840609 (1998-11-01), Hyeon et al.
patent: 5856225 (1999-01-01), Lee et al.
patent: 5856227 (1999-01-01), Yu et al.
patent: 5869396 (1999-02-01), Pan et al.
patent: 5915183 (1999-06-01), Gambino et al.
patent: 6093590 (2000-07-01), Lou
patent: 6177336 (2001-01-01), Lin et al.
patent: 6180501 (2001-01-01), Pey et al.
patent: 6218716 (2001-04-01), Wang et al.
Chhagan Vijai Kumar
Chooi Simon
Gerung Henry
Pradeep Yelehanka Ramachandramurthy
Zhou Mei Sheng
Bowers Charles
Chartered Semiconductor Manufacturing Ltd.
Chen Jack
Pike Rosemary L. S.
Saile George O.
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