Method for forming an ESD protection circuit

Details Method for forming an ESD protection circuit Method for forming an ESD protection circuit

2007-10-23

2007-10-23

Andujar, Leonardo (Department: 2826)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S142000, C438S197000, C257SE21352

Reexamination Certificate

active

10776793

ABSTRACT:
An ESD protection circuit is formed at the input/output interface contact of an integrated circuit to protect the integrated circuit from damage caused by an ESD event. The ESD protection circuit has a polysilicon bounded SCR connected between a signal input/output interface contact of the integrated circuit and a power supply connection of the integrated circuit and a biasing circuit. The biasing circuit is connected to the polysilicon bounded SCR to bias the polysilicon bounded SCR to turn on more rapidly during the ESD event. The biasing circuit is formed by at least one polysilicon bounded diode and a first resistance. Other embodiments of the biasing circuit include a resistor/capacitor biasing circuit and a second diode triggering biasing circuit.

REFERENCES:
patent: 5159518 (1992-10-01), Roy
patent: 5453384 (1995-09-01), Chatterjee
patent: 5629544 (1997-05-01), Voldman et al.
patent: 6534834 (2003-03-01), Ashton et al.
patent: 6580184 (2003-06-01), Song
patent: 6605493 (2003-08-01), Yu
patent: 6610262 (2003-08-01), Peng et al.
patent: 2002/0145164 (2002-10-01), Kunz et al.
patent: 2003/0016479 (2003-01-01), Song
S. Voldman et al., “Electrostatic Discharge (ESD) Protection in Silicon-on-Insulator (SOI) CMOS Technology with Aluminum and Copper Interconnects in Advanced Microprossor semiconductor chips”, EOS/ESD Symposium 99-105, 2A.6.1 to 2A.6.11.
S.Voldman et al., “Semiconductor Process and Structural Optimizaiton of Shallow Trench Isolation-Defined and Polysilicon-Bound Source/Drain Diodes for ESD Networks”, EOS/ESD Symposium 98-151, 3A.1.1 to 3A.1.10.
Umesh Shama et al., “An ESD Protection Scheme for Deep Submicron ULSI Circuits”, 1995 Symp. on VLSI Tech.Digest of Tech.Papers, pp. 85-86.

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