Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-12-21
2001-07-10
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S253000, C438S651000
Reexamination Certificate
active
06258651
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the formation of integrated circuit devices that incorporate both an array of memory cells and an array of logic circuits on a single chip or substrate.
2. Description of the Prior Art
Recently, demand for semiconductor devices has rapidly increased owing to widespread use of integrated electronic circuit. In particularly, as more than hundreds or thousands of electrical components are integrated into the ICs, a mean for higher quality of semiconductor device and more simplification fabrication has become imperative.
For some data processing applications, it has become desirable to provide integrated circuit devices that incorporate on the same chip both arrays of memory cells and arrays of high-speed logic circuits like those typically used in microprocessors or digital signal processors. It might, for example, be desirable to provide an array of dynamic random access memory cells within the integrated circuit device to provide dedicated comparatively high-speed access to a significant amount of data storage for the logical circuits of the integrated circuit device. Applicants that could benefit from the provision of such embedded DRAM include logic circuits that process large amounts of data, such as graphics processors. Providing both high-speed logic circuits and embedded DRAM on the same chip requires that certain aspects of the process flow used for making the chip be dedicated to the formation of logic circuits and that other aspects be dedicated to the formation of memory cells.
FIGS. 1A-1C
illustrate a portion of a process flow that might be used to provide embedded DRAM on an integrated circuit device that includes high speed logic circuits.
FIG. 1A
illustrates an integrated circuit device at an intermediate processing stage that will include embedded DRAM and an array of logic circuits. On the left side of the illustrated device is an exemplary DRAM cell and on the right side of the illustrated device is an exemplary logic FET that makes up part of a logic circuit. Other circuitry for performing input/output (I/O) functions for the integrated circuit device would typically be included but is not shown here.
The embedded DRAM cell, when complete, will include a transfer or pass field effect transistor (FET) coupled to a charge storage capacitor. The transfer FET acts as a switch for selectively coupling the lower electrode of the charge storage capacitor to a bit line so that data can either be read from or stored to the charge storage capacitor. The embedded DRAM and logic circuits of the integrated circuit device are formed on a single silicon substrate
100
, which typically has at least a surface layer of P-type material. Device isolation regions
200
are provided as necessary across the substrate of the device. The illustrated device isolation regions
200
may be fixed oxide regions formed in a modified local oxidation of silicon (LOCOS) process or may be shallow trench isolation (STI) devices consisting of the trenches filled with oxide by chemical vapor deposition (CVD). The illustrated cross section of the embedded DRAM cell includes a section through a transfer FET
400
. Oxide spacer structure
500
are provided on either side of the gate electrode, typically be CVD oxide deposition followed by an etch back process. Oxide spacer structures
500
provide lateral protection to the gate electrode during processing and might also be used in the formation of lightly doped drain (LDD)
600
structures for the source and drain regions of the transfer field effect transistor (FET). Source/drain regions
600
are formed by self aligned ion implantation of N-type dopants on either side of the gate electrode
400
to complete the transfer FET.
Portions of the logic circuitry, schematically illustrated on the right of
FIGS. 1A-1C
, are formed nearly contemporaneously with the formation of the transfer FET of the DRAM array. Depending on design choices, some processing steps may be shared between the embedded DRAM and logic formation process or wholly distinct processes might be used for forming the DRAM and logic circuits. The exemplary FET
400
of the logic circuit is formed on a gate oxide layer
300
and includes a polysilicon gate electrode
400
. It is generally preferred to not provide a self-aligned silicide layer over the polysilicon gate electrode layer
400
at the illustrated stage of the manufacturing process. Instead, it is generally preferred to use a self-aligned silicide (“salicide”) process to form the FET of the logic circuit at a late stage in the manufacturing process. Oxide spacer
500
is formed on either side of the gate electrode
400
and is typically used in defining an LDD structure for the source/drain regions
700
of the logic FET.
After formation of the FET for the DRAM array and the logic array, it is typical to provide a thick oxide layer
800
over the entire substrate
100
. The oxide layer is deposited to a sufficient thickness to both cover the various device structures and to provide a sufficient thickness for the planarization of the oxide layer
800
. Planarization of the oxide layer
800
is important to improve the process latitude for the photolithography and etching steps used to form the charge storage capacitor. After provision of the planarized oxide layer, a via
900
is formed through the planarized oxide layer to expose the source/drain region
700
to which the charge storage of the illustrated DRAM cell will be connected. Doped polysilicon is provided within via
900
to form a vertical interconnect
1050
between the source/drain region
700
and the low electrode
1000
of the charge storage capacitor. The lower electrode
1000
of the charge storage capacitor is typically formed several layers of doped polysilicon. For the design rules typically used in modern processes, it is important to provide a three dimensional crown or fin capacitor structure for the lower electrode
1000
so that it has sufficient surface area to provide a sufficient level of charge storage for the capacitor. Such a crown or fin structure is necessary to ensure that the charge storage capacitor of the DRAM cell stores a sufficiently large charge to facilitate data reading and writing operations as well as to ensure that the stored charge remains on the charge storage capacitor for an acceptable amount of time without requiring a refresh operation. Formation of the charge storage capacitor continues by providing a capacitor dielectric layer
1100
consisting of the three layer oxide
itride/oxide structure known as ONO over the lower capacitor electrode
1000
. An upper electrode
1200
is formed by providing another layer of doped polysilicon, which is patterned in a manner conventional to DRAM arrays. The completed charge storage capacitor is shown in FIG.
1
B.
After completion of the charge storage capacitor, a mask such as photoresist mask
1300
is provided over the
FIG. 1B
device to cover the embedded DRAM array and to expose the oxide layer
800
over the array of logic circuitry. Etching is performed to remove the thick oxide layer
800
from above the logic circuitry, resulting in the structure shown in FIG.
1
C. Processing continues on the logic FET to form a silicide layer
1400
over the gate electrode
400
and silicide layers
1400
over the source/drain regions
700
. The silicide layer
1400
reduces the resistivity and contact resistance of the gate electrode and the source/drain regions. Typically, the silicide layers are formed in a self-aligned (“salicide”) process in which a layer of a refractory metal such as titanium is deposited over the exposed polysilicon gate electrode and the exposed silicon source/drain regions. An initial anneal is performed to convert a portion of the deposited metal layer to a metal silicide. An etch is performed to convert unreacted metal and then a second anneal is performed to achieve a low resistivity for the metal silicide layers
1400
on the gate electrode and source/drain regions. Process
Jenq Jason Jyh-shyang
Lee Hal
Tsai Jey
United Microelectronics Corp.
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