Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2008-07-22
2008-07-22
Lindsay, Jr., Walter L (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S300000, C257SE21632, C257SE21668
Reexamination Certificate
active
11152931
ABSTRACT:
An electronic device is formed by forming a first and second layer overlying a plurality of transistor locations. An etch is performed to remove portions of the first and second layers to expose a portion of the plurality of transistor locations, while other portions of the first and second layer remain to protect other transistor locations. Subsequently, source/drain locations of the exposed transistor locations are etched along with the remaining portion of the second layer. The etch is substantially terminated by removing the portion of the second layer using an end-point detection technique involving the first layer. Subsequently an epitaxial layer is formed in the source/drain recesses to provide stress on a channel region of the transistor locations.
REFERENCES:
patent: 4963502 (1990-10-01), Teng et al.
patent: 6074904 (2000-06-01), Spikes et al.
patent: 6621131 (2003-09-01), Murthy et al.
patent: 2003/0111708 (2003-06-01), Hwang et al.
patent: 2005/0087824 (2005-04-01), Cabral et al.
patent: 2006/0246641 (2006-11-01), Kammler et al.
patent: 2006/0286736 (2006-12-01), Orlowski et al.
patent: 2007/0184600 (2007-08-01), Zhang et al.
patent: 2007/0264765 (2007-11-01), Lan et al.
Thompson et al., “In Search of ‘Forever,’ Continued Transistor Scaling One New Material at a Time,” IEEE Transactions on Semiconductor Manufacturing, vol. 18, No. 1, IEEE, pp. 26-36, Feb. 2005.
Mistry et al., “Delaying Forever: Uniaxial Strained Silicon Transistors in a 90nm CMOS Technology,” 2004 Symposium on VLSI Technology Digest of Technical Papers, 2004 IEEE, pp. 50-51.
Ghani et al., “A 90nm High Volume Manufacturing Logic Technology Featuring Novel 45nm Gate Length Strained Silicon CMOS Transistors,” 2003 IEEE, pp. 978-980.
Chidambaram et al., “35% Drive Current Improvement from Recessed-SiGe Drain extensions on 37nm Gate Length PMOS,” 2004 Symposium on VLSI Technology Digest of Technical Papers, 2004 IEEE, pp. 48-49.
Goolsby Brian J.
Orlowski Marius K.
Freescale Semiconductor Inc.
Lindsay, Jr. Walter L
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