Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-09-07
2002-09-17
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S119000, C438S200000, C438S201000, C438S258000, C438S266000, C438S275000, C438S276000
Reexamination Certificate
active
06451652
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductors. In particular, the present invention relates to forming an EEPROM cell together with transistors for peripheral circuits.
2. The Prior Art
Background
In the art of semiconductor manufacturing, the usual practice in defining transistor gates is to deposit the conducting gate material and then form a layer of photosensitive material, which is usually referred to as photoresist, on top of the conducting material. The photoresist is selectively exposed to light and then chemically treated to “develop” the resist in order to leave the photoresist in only the regions in which it is desired to form the gate electrodes. Subsequent to the development step, the gate electrode material is etched to remove it from the regions not protected by photoresist.
In recent applications, an electrode may be formed that provides select gates in the regions on the two sides of an underlying floating gate electrode and also acts to partially control the potential on the floating gate via capacitive coupling. This electrode is often referred to as the control gate electrode.
U.S. Pat. No. 5,986,931, assigned to one of the inventors of this patent, describes such a nonvolatile memory cell structure such and is shown in FIG.
1
. The cell consists of a floating gate
122
, i.e. a gate without direct electrical connection, formed on a first layer of polysilicon overlapped by a second layer of polysilicon
120
which acts as a control gate. There is a thin layer of silicon oxide
130
between the floating gate and an n-well formed in the substrate. The floating gate is separated from the control gate by a dielectric layer
132
, which is often formed of a sandwich structure consisting of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer. The control gate is separated from the n-well in the regions of direct overlap by two dielectric layers
134
and
136
which are thicker than the oxide layer
130
so that the can withstand the potential of greater than 10 V that is applied between the control gate and n-well during programming.
There is an active region
108
that is surrounded by thick oxide which acts as isolation to separate the transistors from those in neighboring cells. The portions of the active region not covered by polysilicon, are doped heavily p-type to form a drain
126
and a source
128
for the cell transistors. The cell contains three transistors in series. There is a select transistor between drain
126
and floating gate; the channel of this transistor lies in the active region under the dielectric
134
. There is a floating gate memory transistor whose channel region lies in the active region under the thin oxide
130
. There is a virtual source/drain between the drain select transistor and the floating gate transistor. The channel of a second select transistor is formed in the active region under the dielectric
136
. Diffusion
128
is the source for the source select transistor.
As is discussed therein, the voltage between source and drain on this cell never exceeds 1-2 V in normal operation. Because of this, the channel length of the two select transistors can be quite short without the applied source-drain bias causing punch through. It is desirable to make the select transistors as short as possible without adverse electrical effects because this both allows the cell to be smaller and increases the magnitude of the current through a conducting cell during read.
However, certain problems arise in manufacturing the cell of
FIG. 1
as the select gates become very short. On the one hand, if the select gates become shorter than the misalignment between the photoresist pattern that defines the control gate electrode and the floating gate, complete etching of the control gate conductor layer results in exposing one side of the floating gate while the control gate on the other side is longer than twice the designed length of the floating gate. Both of these effects are undesirable.
Additionally, exposing one side of the floating gate changes the capacitive coupling between the floating gate and the control gate. Furthermore, forming a control gate on one side of the floating gate that is longer than the design length of the two control gates, one on each side of the floating gate, will reduce the read current. Finally, it is known that it is difficult to completely remove a conducting layer from the side of a vertical feature with the result that what are referred to as stringers remain along the side of a vertical feature.
The prior art has been deficient in forming the structure of
FIG. 1
without encountering these difficulties.
It has been previously suggested that the “stringer” can be used to form an electrode along one side of a gate electrode. Such a process may be found in A. T. Wu, et al, “A Novel High-Speed, 5-Volt Programming EPROM Structure”, IEDM Technical Digest, pp. 584-7, (1986). The approach suggested by Wu el al contemplates removing the conducting material from atop the first gate electrode in a maskless operation.
Hence, there is need for a process for forming a semiconductor device whereby a photomask is employed in conjunction with the use of “stringers” to form a control gate that has well defined capacitive coupling to the floating gate as well as select gates in series with the floating gate of well defined length.
BRIEF DESCRIPTION OF THE INVENTION
The invention satisfies the above needs. The present invention relates generally to semiconductors. In particular, the present invention relates to forming an EEPROM cell together with transistors for peripheral circuits.
A method for forming an EEPROM cell together with transistors for peripheral circuits is disclosed. A method according to one aspect of the invention comprises providing a semiconductor substrate, a gate dielectric layer disposed over said substrate, an electrode disposed over said gate dielectric layer, where the electrode is further enveloped in an electrode dielectric layer, and a select gate dielectric layer is disposed on either side of the electrode dielectric layer; conformally depositing a conductive layer over the electrode dielectric layer and the gate dielectric layers; coating the conductive layer with photoresist; selectively exposing the photoresist to radiation to form a sidewall over the electrode; anisotropically etching the conductive layer; and whereby the method is characterized in that a predetermined amount of material remains proximate to the edge of the electrode forming a structure that extends a short distance beyond the sides of the electrode.
Additional aspects of the above method include conformally depositing a conductive layer over the electrode dielectric layer and the gate dielectric layers such that the conformal deposit forms a sidewall over the electrode and the electrode enveloping dielectric layer, where the conductive layer extends beyond the edge of the electrode dielectric by an amount equal to the thickness of the conducting layer.
A further aspect of the present invention is disclosed wherein the act of coating said conductive layer with photoresist is further characterized in that the photoresist is positioned such that the edge of the photoresist lies between the outer edge of the electrode dielectric layer and the sidewall of the conductive layer. Yet a further aspect is disclosed wherein the vertical thickness of the sidewall is approximately equal to the sum of the thickness of the electrode, the thickness of the conducting layer, and the thickness of the electrode dielectric layer.
An additional aspect of the present invention is disclosed, wherein the act of anisotropically etching the conductive layer removes an amount of material equal in thickness to the thickness of the conducting layer+&Dgr;, where &Dgr;<the sum of the thickness of the electrode+the thickness of the gate dielectric layer. A may be chosen to be 20% to 30% of the thickness of the conductive layer. The etching of the conductive l
Caywood John
Spadea Gregorio
Sierra Patent Group Ltd.
The John Millard and Pamela Ann Caywood 1989 Revocable Living Tr
Yevsikov V.
LandOfFree
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