Method for forming an asymmetric floating gate overlap for impro

Details Method for forming an asymmetric floating gate overlap for impro Method for forming an asymmetric floating gate overlap for impro

1994-11-10

2000-09-26

Booth, Richard

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438286, H01L 218247

Patent

active

061241687

ABSTRACT:
A method of making an electrically erasable non-volatile EPROM memory device and the device itself having an asymmetric floating gate with respect to a buried source region and a buried drain region is disclosed. A patterned floating gate member is formed over a portion of the source region and a portion of the drain region producing a floating gate-to-source overlap and a floating gate-to-drain overlap, respectively, such that the floating gate-to-source overlap is less than the floating gate-to-drain overlap.

REFERENCES:
patent: 4698787 (1987-10-01), Mukherjee et al.
patent: 4780424 (1988-10-01), Holler et al.
patent: 5028979 (1991-07-01), Mazzali
Wolf et al., "Silicon Processing for the VLSI Era vol. 1: Process Technology", pp. 1-5, Lattice Press, 1986.
Wolf, "Silicon Processing for the VLSI Era, vol. II, Process Integration", pp. 629-631, 1990.

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