Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2005-08-09
2005-08-09
Le, Dung A. (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S003000, C438S253000, C438S396000, C257S295000, C257S310000
Reexamination Certificate
active
06927120
ABSTRACT:
Asymmetrically structured memory cells and a fabrication method are provided. The method comprises: forming a bottom electrode; forming an electrical pulse various resistance (EPVR) first layer having a polycrystalline structure over the bottom electrode; forming an EPVR second layer adjacent the first layer, with a nano-crystalline or amorphous structure; and, forming a top electrode overlying the first and second EPVR layers. EPVR materials include CMR, high temperature super conductor (HTSC), or perovskite metal oxide materials. In one aspect, the EPVR first layer is deposited with a metalorganic spin coat (MOD) process at a temperature in the range between 550 and 700 degrees C. The EPVR second layer is formed at a temperature less than, or equal to the deposition temperature of the first layer. After a step of removing solvents, the MOD deposited EPVR second layer is formed at a temperature less than, or equal to the 550 degrees C.
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patent: 6534326 (2003-03-01), Hsu et al.
Article entitled, “Electric-Pulse-Induced Reversible Resistance Change Effect in Magnetoresistive Films”, by S. Q. Liu, N. J. Wu and A. Ignatiev, published in Applied physics Letters, vol. 76, No. 19, May 8, 2000, pp 2749-2751.
Evans David R.
Hsu Sheng Teng
Li Tingkal
Pan Wei
Zhuang Wei-Wei
Curtin Joseph P.
Le Dung A.
Ripma David C.
Sharp Laboratories of America Inc.
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