Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-12-04
2003-06-17
Chaudhuri, Olik (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S296000, C438S297000, C438S591000, C438S783000
Reexamination Certificate
active
06579767
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor device; and, more particularly, to a method for manufacturing a gate structure incorporated therein aluminum oxide as a gate dielectric.
DESCRIPTION OF THE PRIOR ART
As is well known, a semiconductor device has been down-sized by a scale down of a design rule. Therefore, a gate oxide tends to rapidly approach 30 Å in thickness and below to increase the capacitance between a gate electrode and a channel region. However, the use of silicon dioxide as a gate dielectric is limited at this thickness and below. Once silicon dioxide SiO
2
is formed to a thickness of less than 30 Å, direct tunneling may occur through the gate dielectric to the channel region, thereby increasing a leakage current associated with the gate electrode and the channel region, causing an increase in power consumption.
Since reducing the thickness of the gate dielectric inherently increases the gate-to-channel leakage current, alternative methods have been developed to reduce this leakage current while maintaining thin SiO
2
equivalent thickness. One of these methods is to use a high K dielectric material such as Ta
2
O
5
as the gate dielectric material to increase the capacitance between the gate and the channel.
However, if a poly-silicon is utilized as a gate electrode, the use of Ta
2
O
5
for gate dielectric materials has a disadvantage in integrating the semiconductor device. That is, an undesired SiO
2
and TaSi
2
are formed at an interface between Ta
2
O
5
and the poly-silicon, which, in turn, increases an equivalent oxide thickness. In order to overcome this problem, a barrier metal such as TiN is employed. However, the TiN makes a threshold voltage shift changed.
In addition, the use of high K dielectrics for gate dielectric materials is disadvantageous in integrated circuits because high dielectric materials contain great number of bulk traps and interface traps than gate dielectrics made from thermally grown SiO
2
. These traps adversely effect sub-threshold slope and threshold voltage operation of electric devices.
If the above-described problems are overcome, a high K dielectric is utilized as a gate oxide with excellent leakage current as well as a low interface state with both a gate electrode and a silicon substrate.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a method for manufacturing a gate structure incorporated therein aluminum oxide as a gate oxide for use in a semiconductor device.
In accordance with one aspect of the present invention, there is provided a method for manufacturing a gate structure for use in a semiconductor device, the method comprising the steps of: a) preparing a semiconductor substrate provided with an isolation region formed therein; b) forming an aluminum oxide (Al
2
O
3
) layer on top of the semiconductor substrate with doping a dopant in situ; c) forming a conductive layer on top of the Al
2
O
3
layer; and d) patterning the conductive layer, thereby obtaining the gate structure.
In accordance with another aspect of the present invention, there is provided a method for method for manufacturing a gate structure for use in a semiconductor device, the method comprising the steps of: a) preparing a semiconductor substrate provided with an isolation region formed therein; b) forming an Al
2
O
3
layer on top of the semiconductor substrate; c) forming a conductive layer on top of the Al
2
O
3
layer; d) implanting dopants into the Al
2
O
3
layer; e) patterning the conductive layer and the Al
2
O
3
layer into the gate structure; and f) selectively reoxidizing the dopants.
REFERENCES:
patent: 3642545 (1972-02-01), Pammer et al.
patent: 3766637 (1973-10-01), Norris et al.
patent: 3775262 (1973-11-01), Heyerdahl
patent: 4460413 (1984-07-01), Hirata et al.
patent: 4566173 (1986-01-01), Gössler et al.
patent: 5079184 (1992-01-01), Hatano et al.
patent: 5923056 (1999-07-01), Lee et al.
Cho Hung-Jae
Jang Se-Aug
Kim Jung-Ho
Lee Jeong-Youb
Park Dae-Gyu
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Garcia Joannie
Hyundai Electronics Industries Co,. Ltd.
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