Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1996-09-23
1999-03-02
Niebling, John F.
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438217, 438370, H01L 218238
Patent
active
058770496
ABSTRACT:
A novel MOS transistor structure for improving device scaling by improving short channel control includes a buried back gate beneath a channel region of the MOS transistor. A separate contact to a well that is electrically communicated to the buried back gate improves short channel controls without performance degradations. In a preferred embodiment, the back gate is grounded when turning the n-channel MOS transistor off. In alternate embodiments, the buried layer produces retrograde p wells. In some applications, multiple buried layers may be used, with one or more being planar. CMOS devices may have independent, multiple buried back gates.
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patent: 5191401 (1993-03-01), Shirai et al.
patent: 5247200 (1993-09-01), Momose et al.
patent: 5489540 (1996-02-01), Liu et al.
patent: 5608253 (1997-03-01), Liu et al.
Chang Kuang-Yeh
Liu Yowjuang W.
Advanced Micro Devices , Inc.
Murphy John
Niebling John F.
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