Method for forming a vertical nitride read-only memory

Details Method for forming a vertical nitride read-only memory Method for forming a vertical nitride read-only memory

2003-06-19

2003-12-30

Lebentritt, Michael S. (Department: 2824)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S266000, C438S257000, C438S275000, C438S259000

Reexamination Certificate

active

06670246

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to a method for forming a non-volatile memory cell. More particularly, it relates to a method for forming a vertical nitride read-only memory (NROM) cell to increase performance thereof.
2. Description of the Related Art
The non-volatile memory industry began development of nitride read-only memory (NROM) in 1996. This relatively new non-volatile memory technology utilizes oxide-nitrideoxide (ONO) gate dielectric and known mechanisms of programming and erasing to create two separate bits per cell. Thus, the NROM bit size is half of the cell area. Since silicon die size is the main element in the cost structure, it is apparent that NROM technology is an economic breakthrough.
FIG. 1
is a cross-section showing a conventional NROM cell structure. This cell includes a silicon substrate
100
which has two separated bit lines (source and drain)
102
, two bit line oxides
104
formed over each of the bit lines
102
, respectively, and an ONO layer
112
having a silicon nitride layer
108
sandwiched between the bottom silicon oxide layer
106
and the top silicon oxide layer
110
formed on the substrate
100
between the bit line oxides
102
. A gate conductive layer
114
(word line) lies on the top of the bit line oxides
104
and the ONO layer
112
.
The silicon nitride layer
108
in the ONO structure
112
has two chargeable areas
107
and
109
adjacent to the bit lines
102
. These areas
107
and
109
are used for storing charges during memory cell programming. To program the left bit close to area
107
, left bit line
102
is the drain and receives the high programming voltage. At the same time, right bit line
102
is the source and is grounded. The opposite is true for programming area
109
. Moreover, each bit is read in a direction opposite its programming direction. To read the left bit, stored in area
107
, left bit line
102
is the source and right bit line
102
is the drain. The opposite is true for reading the right bit, stored in area
109
. In addition, the bits are erased in the same direction that they are programmed.
Increasing cell density for integration of ICs requires reducing the bit line area or shrinking the width of the ONO layer. Unfortunately, reducing bit line area may increase the resistance of the bit line, and result in lower operation speed of the memory cell. In addition, shrinking the gate length may induce cell disturbance during programming, erasing, or reading, in particular, when the width of the gate length is less than 10 nm. Therefore, the cell density is limited.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide a novel method for forming a vertical nitride read-only memory (NROM) cell, which uses the sidewall of the substrate trench as a channel of the NROM cell, reducing the resistance of bit lines. Moreover, a vertical channel is formed instead of the conventional planar one, thereby preventing the cell disturbance during programming, erasing, and reading.
According to the object of the invention, the invention provides a method for forming a vertical NROM cell. First, a substrate having at least one trench is provided and then a masking layer is formed over the sidewall of the trench. Next, ion implantation is performed on the substrate to respectively form doping areas in the substrate near its surface and the bottom of the substrate trench to serve as bit lines. Next, bit line oxides are formed over each of the doping areas and an oxide layer is formed overlying the mask layer by thermal oxidation. Finally, a conductive layer is formed overlying the bit line oxides and fills in the trench to serve as a word line.
The bit lines can be formed by phosphorus ion implantation. Moreover, the masking layer comprises an oxide layer and an overlying nitride layer. The word line can be polysilicon.


REFERENCES:
patent: 5210047 (1993-05-01), Woo et al.
patent: 6404020 (2002-06-01), Kim
patent: 6432778 (2002-08-01), Lai et al.
patent: 6440798 (2002-08-01), Lai et al.
patent: 6468868 (2002-10-01), Lee et al.
patent: 6486028 (2002-11-01), Chang et al.
patent: 6548861 (2003-04-01), Palm et al.
patent: 6620693 (2003-09-01), Lai et al.

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