Method for forming a v-shaped floating gate

Details Method for forming a v-shaped floating gate Method for forming a v-shaped floating gate

1999-10-08

2001-06-19

Elms, Richard (Department: 2824)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S254000, C438S257000

Reexamination Certificate

active

06248631

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to non-volatile digital memory, and more particularly, to FLASH EPROM memory incorporating novel floating gates having reduced lateral dimensions.
2. Description of Related Art
FLASH EPROM memory is a class of non-volatile storage integrated circuits. In general, FLASH EPROMS have the capability of electrically erasing, programming, or reading a memory cell on a chip. Generally, a FLASH EPROM includes a floating gate and a control gate which form an electrical connection. A FLASH EPROM operates by charging or discharging electrons in the floating gate of the memory cell in a capacitive manner. The floating gate is formed of a conductive material, typically made of polysilicon, which is insulated from the channel of the transistor by a layer of oxide or other insulating material, and insulated from the control gate or word-line of the transistor by a second layer of insulating material.
The act of charging the floating gate is termed a Aprogram@ step for a FLASH EPROM. The program step may be accomplished through so-called hot electron injection by establishing a large positive voltage between the control gate and the source. The act of discharging the floating gate is called the Aerase@ function for a FLASH EPROM. The erase function is typically carried out by an F-N tunneling mechanism between the floating gate and the source of the transistor (source erase) or between the floating gate and the substrate (channel erase).
Due to increasing memory demands, a need exists to further reduce the size of memory devices, such as FLASH EPROMs. Reducing the cell size of memory devices increases performance and reduces power consumption.
Several devices have been developed with reduced cell size. One such device is described in AA Low Voltage Operating Flash Memory Cell with High Coupling Ratio Using Horned Floating Gate with Fine HSG,@ by Kitamura et al., 1998
Symposium on VLSI Technology Digest of Technical Papers
. Another example of a memory device with reduced cell size is described in AA 0.24-Fm Cell Process With 0.18-Fm Width Isolation and 3D Interpoly Dielectric Films for 1-GB Flash Memories@ by Kobayashi et al.,
IEEE
97-275 (1997).
Reducing the size of a memory cell has led to memory cells with certain disadvantages including overbearing floating gates, or intermediate structures formed during the manufacturing of the floating gate, which degrade the tunnel oxide layer. The formation of sharp comers on the floating gate also leads to charge leakage.
SUMMARY OF THE INVENTION
An embodiment of this invention provides a floating gate memory cell, where the floating gate comprises a first lateral end region and a second lateral end region. A middle region is positioned towards a middle of the floating gate with respect to the first lateral end region and the second lateral end region. The thickness of the floating gate decreases continuously from at least one of the first or second lateral end regions to the middle region.
Another embodiment of the invention provides for a floating gate in a floating gate memory cell. The floating gate includes a first polysilicon material deposited in a first fabrication step to extend from a first lateral end to a second lateral end. A second polysilicon material is deposited over the first polysilicon material to form a first tapered sidewall adjacent to the first lateral end, and a second tapered sidewall adjacent to the second lateral end. A third polysilicon material is deposited in a third fabrication step over at least the first or second polysilicon material to extend from the first lateral end to the second lateral end.
In regard to any of the embodiments, a variation may provide for the thickness of the floating gate to be substantially symmetrical about the middle region of the floating gate. A symmetrical distribution of thickness enables a three dimensional contour to be developed for the floating gate that has a minimum thickness centrally positioned with respect to lateral ends having a maximum thickness.
Another variation to the above embodiments may provide for a floating gate to be formed from a first polysilicon material deposited in a first fabrication step, a second polysilicon material deposited at the lateral end regions in a second fabrication step, and a third polysilicon material deposited in a third fabrication step. As will be further described, the third polysilicon material may be deposited to adapt a contour formed from polysilicon material deposited in a first and second step.
Another variation to the above embodiments may provide for the first and second lateral end regions to be formed from the first, second and third polysilicon materials, and the middle region to be formed from the first and third polysilicon materials.
Another variation to the above embodiments may provide the first and second lateral end regions to each have a uniform thickness across a top surface distal to an underlying substrate. The first and second lateral end regions may also be formed as peaks.
The floating gates of the above embodiments may each also be provided in a floating gate memory cell, where the floating gate memory cell includes a substrate, source and drain regions positioned over the substrate, an insulating layer positioned over the source and drain regions, and a floating gate positioned over the insulating layer between the source and drain regions.
The invention also relates to methods of forming a contoured floating gate for use in a floating gate memory cell. One embodiment of the method includes forming a polysilicon structure between a first alignment structure and a second alignment structure, where the polysilicon structure has a maximum thickness at a first lateral end region adjacent to the first alignment structure and at a second lateral end region adjacent to the second alignment structure, and where the polysilicon structure has a minimum thickness at a middle region positioned between the first lateral end regions and the second lateral end region. The method further includes forming a polysilicon layer over the polysilicon structure such that the polysilicon layer adopts a contour of the polysilicon structure.
The method may further include forming a polysilicon structure between a first alignment structure and a second alignment structure by depositing a first polysilicon layer over the substrate, and by depositing a second polysilicon layer over the first polysilicon layer so that the second polysilicon layer has a maximum thickness at the first lateral end region and at the second lateral end region.
In another embodiment, a method is provided which includes forming a first polysilicon structure by depositing a first polysilicon layer over a substrate underlying the contoured floating gate between the first and second alignment structure, and forming a second polysilicon layer over a topography defined by the first alignment structure, the second alignment structure, and the first polysilicon layer. The method further includes removing the second polysilicon layer from the first and second alignment structure after depositing the second polysilicon layer over the topography, and forming a third polysilicon layer over the second polysilicon such that the third polysilicon layer adopts a contour of the second layer.
The method may further include forming a polysilicon structure by removing a portion of the second polysilicon layer from the middle region.
Another embodiment of the invention includes forming a polysilicon structure by removing a portion of the first polysilicon layer in a process to remove the portion of the second polysilicon layer from the middle region.
Another embodiment of the invention includes forming a polysilicon structure by removing a portion of the second polysilicon layer from the middle region so that a remaining portion of the second polysilicon layer has a sloped thickness with a maximum thickness at the first lateral end region and at the second lateral end regi

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