Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Multiple layers
Reexamination Certificate
2000-06-19
2001-02-06
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Multiple layers
C430S416000, C430S416000
Reexamination Certificate
active
06184155
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to form a silicon dioxide, gate insulator layer, for a metal oxide semiconductor field effect transistor, (MOSFET), device.
(2) Description of Prior Art
The advent of micro-miniaturization, or the use of sub-micron features, for MOSFET devices, have necessitated the use of ultra-thin, gate insulator layers. For example, the use of 0.13 um, (or channel lengths of 0.13 um), technology, results in a projected gate insulator layer, with a thickness in the range of 10 to 20 Angstroms. The use of these ultra-thin gate insulator layers, such as thermally grown silicon dioxide, can present unacceptable leakage rates, during the operation of the 0.13 um MOSFET device. In addition significant, and unacceptable, gate insulator leakage can occur during the standby, or off mode, of the narrow channel length MOSFET device.
This invention will teach a process for forming ultra-thin, silicon dioxide gate insulator layers, in which the leakage rate of the thin silicon dioxide layer is reduced, when compared to counterparts formed without the use of the process described in this present invention. Prior art, such as Gdula et al, in U.S. Pat. No. 3,925,107, describe a post-oxidation, anneal process, which reduces the fixed charge, and fast states, in silicon dioxide, gate layers as thin as 100 Angstroms. However that prior art does not teach the novel process, now presented, allowing ultra-thin, silicon dioxide layers to be used for sub-micron MOSFET devices, featuring reductions in leakage currents, when compared to counterparts fabricated without the benefit of this invention.
SUMMARY OF THE INVENTION
It is an object of this invention to fabricate an MOSFET device featuring a silicon dioxide gate insulator between about 10 to 20 Angstroms in physical thickness.
It is another object of this invention to employ a gate insulator layer formation process, featuring the attainment of an initial silicon dioxide layer, formed via a first, in situ steam generated, (ISSG), growth, and in situ anneal procedure, followed in situ, by a second, ISSG growth, and another in situ anneal procedure, resulting in a final silicon dioxide layer.
It is still another object of this invention to perform the in situ anneal cycles, for the first, and for the second ISSG growth and in situ anneal procedures, in a nitrous oxide, (NO), ambient.
In accordance with the present invention a method of forming an ultra-thin, (between about 10 to 20 Angstrom), silicon dioxide layer, for use as a gate insulator layer in narrow channel length MOSFET devices, is described. After formation of a well region, in a semiconductor substrate, a silicon dioxide layer is formed using a two step procedure. An first, in situ steam generation, (ISSG), procedure is used to establish an initial silicon dioxide layer, with the first ISSG procedure comprised of an oxidation step, followed by an in situ anneal, performed in a nitrous oxide ambient. A second, ISSG procedure, is next performed in situ, again comprised of a oxidation procedure, followed by another in situ, nitrous oxide anneal. Formation of a gate structure; a lightly doped source/drain regions; insulator spacers on the sides of the gate structure; and a heavily doped source/drain region; complete the fabrication of the narrow channel MOSFET device, featuring a silicon dioxide gate insulator layer, obtained via a two step, ISSG procedure.
REFERENCES:
patent: 3925107 (1975-12-01), Gdula et al.
patent: 4140548 (1979-02-01), Zimmer
patent: 5244843 (1993-09-01), Chau et al.
patent: 5591681 (1997-01-01), Wristers et al.
patent: 5817581 (1998-10-01), Bayer et al.
patent: 5891809 (1999-04-01), Chau et al.
patent: 5940736 (1999-08-01), Brady et al.
patent: 5972779 (1999-10-01), Jang
patent: 6114258 (2000-09-01), Miner et al.
Jang Syun-Ming
Liang Mong-Song
Yu Mo-Chiun
Ackerman Stephen B.
Ghyka Alexander G.
Niebling John F.
Saile George O.
Taiwan Semiconductor Manufacturing Company
LandOfFree
Method for forming a ultra-thin gate insulator layer does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for forming a ultra-thin gate insulator layer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming a ultra-thin gate insulator layer will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2576769