Method for forming a transistor with selective epitaxial growth

Details Method for forming a transistor with selective epitaxial growth Method for forming a transistor with selective epitaxial growth

1999-12-21

2000-12-26

Nelms, David

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438305, H01L 21336

Patent

active

06165857&

ABSTRACT:
A new improvement for selective epitaxial growth is disclosed. In one embodiment, the present invention provides a low power metal oxide semiconductor field effect transistor (MOSFET), which includes a substrate. Next, a gate oxide layer is formed on the substrate. Moreover, a polysilicon layer is deposited on the gate oxide layer. Patterning to etch the polysilicon layer and the gate oxide layer to define a gate. First ions are implanted into the substrate by using said gate as a hard mask. Sequentially, a liner oxide is covered over the entire exposed surface of the resulting structure. Moreover, a conformal first dielectric layer and second dielectric layer are deposited above the liner oxide in proper order. The second dielectric layer is etched back to form a dielectric spacer on sidewall of the first dielectric layer. Next, the first dielectric layer is etched until upper surface of the gate and a portion of the substrate are exposed, wherein a part of the second dielectric layer is also etched accompanying with etching a part of the first dielectric layer. Further, second ions are implanted into the exposed substrate to form a source/drain region. A conductive layer is selectively formed on said over the exposed gate and source/drain. Finally, a self-aligned silicide layer is formed over the conductive layer.

REFERENCES:
patent: 5652156 (1997-07-01), Liao et al.
patent: 5882973 (1999-03-01), Gardner et al.
patent: 6015753 (2000-01-01), Lin et al.

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