Method for forming a test structure to determine the effect of L

Details Method for forming a test structure to determine the effect of L Method for forming a test structure to determine the effect of L

1997-08-18

1999-06-01

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438529, H01L 21336

Patent

active

059083158

ABSTRACT:
The present invention advantageously provides a method for forming a test structure for determining how LDD length of a transistor affects transistor characteristics. In one embodiment, a first polysilicon gate conductor is provided which is laterally spaced from a second polysilicon gate conductor. The gate conductors are each disposed upon a gate oxide lying above a silicon-based substrate. An LDD implant is forwarded into exposed regions of the substrate to form LDD areas within the substrate adjacent to the gate conductors. A first spacer material is then formed upon sidewall surfaces of both gate conductors to a first pre-defined thickness. Source/drain regions are formed exclusively within the substrate a spaced distance from the first gate conductor, the spaced distance being dictated by the first pre-defined thickness. A second spacer material is formed laterally adjacent to the first spacer material to a second pre-defined distance. Source/drain regions are then formed within the substrate a spaced distance from the second gate conductor, the spaced distance being dictated by the second predefined thickness. The resulting transistors have a mutual source/drain region between them. More transistors may also be fabricated in a similar manner.

REFERENCES:
patent: 5480814 (1996-01-01), Wuu et al.
patent: 5716866 (1998-02-01), Dow et al.
patent: 5804497 (1998-09-01), Gardner et al.

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