Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
1997-11-24
2001-09-04
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S592000, C438S153000
Reexamination Certificate
active
06284633
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor manufacturing, and particularly to formation of a gate stack of a semiconductor device having a particular structure.
BACKGROUND OF THE INVENTION
FIG. 1
illustrates a prior art gate stack, particularly a high performance gate stack associated with logic devices and memory cells such as static random access memories (SRAMs). The gate stack
5
includes a substrate
10
, a gate oxide layer
12
, a composite conductive gate layer
13
, including first poly layer
14
, second poly layer
16
, and tungsten silicide layer
18
. The poly layers
14
,
16
are formed of polycrystalline silicon, as is well known in the art.
According to the prior art, the structure is subjected to a rapid thermal anneal step, generally at a temperature above 850° C., so that the tungsten silicide layer
18
changes phases, from an amorphous phase to a tetragonal crystalline phase. This phase change is effective in lowering the sheet resistance of the composite conductive gate layer
13
(e.g., 80 to 20 ohms per square). After the rapid thermal anneal step is carried out, a silicon glue layer
20
is formed on the tungsten silicide layer
18
, as shown in FIG.
2
. Next, an anti-reflective coating (ARC) layer
22
is formed over the silicon glue layer
20
. The function of the silicon glue layer
20
is to provide an interfacial layer whereby the subsequently formed ARC layer
22
adheres to the tungsten silicide layer
18
. As is known in the art, the ARC layer
22
is formed to prevent unwanted and detrimental reflection of energy during subsequent photolithography steps. Next, a silicon nitride layer
24
is formed. The silicon nitride layer acts as an etch stop layer in subsequent etch steps and insulates the gate stack from conductive layers that form contacts that are dropped thereon to active regions (not shown) of the substrate
10
. The silicon nitride layer
24
is formed by LPCVD (low-pressure chemical vapor deposition) as is well known in the art.
The present inventors have recognized numerous problems associated with the gate structure illustrated in
FIGS. 1 and 2
, including poly depletion and out-gassing. Poly depletion occurs when dopants implanted into the poly layers
14
,
16
are out-gassed during the rapid thermal anneal step noted above. For example, if the poly layers
14
,
16
of gate stack
5
have been doped with phosphorous, the rapid thermal anneal step causes the phosphorous to out-gas. This out-gassing causes build-up of phosphorous pentaoxide along the chamber walls, and an increase in sheet resistance of the composite conductive gate layer
13
. This build-up causes problems during subsequent annealing steps of other materials. For example, other materials including Ti, TiN and W that are used for formation of tungsten plugs. The phosphorous pentaoxide build-up in the anneal chamber migrates and contaminates the structure during heating. Such contamination causes voids in the tungsten during plug deposition, resulting in reduced reliability of the semiconductor device.
In addition to phosphorous, other dopants such as arsenic can also lead to contamination of the Ti/TiN layers. Further, use of arsenic raises additional health and safety concerns that must be addressed during purge cycles and chamber cleaning processes. One method that has been considered to address the out-gassing issue calls for provision of a dedicated anneal chamber for steps where out-gassing occurs. However, this results in increased manufacturing costs and does not resolve the issues associated with the safety and cleaning of such tools.
Further, the inventors investigated another method for addressing the out-gassing and poly depletion issues with respect to the prior art. Particularly, the inventors considered forming the silicon glue layer
20
, the ARC layer
22
, and the silicon nitride layer
24
prior to rapid thermal anneal. However, it was found that those layers peeled from the gate stack, which was believed to be due to the intrinsic compressive stress of the silicon nitride layer
24
. Accordingly, this particular process flow was not a viable solution to the out-gassing and poly depletion of the prior art.
An additional drawback of the prior art is the required number of steps used in forming the layers illustrated in FIG.
2
. Specifically, the steps of forming the silicon glue layer
20
, the ARC layer
22
, and the nitride layer
24
are laborious and expensive.
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Boeck Bruce
Filipiak Stanley M.
Nagabushnam Rajan
Abel Jeffrey S.
Chaudhuri Olik
Motorola Inc.
Peralta Ginette
Rodriguez Robert A.
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