Method for forming a T-gate for better salicidation

Details Method for forming a T-gate for better salicidation Method for forming a T-gate for better salicidation

1999-11-05

2001-09-04

Trinh, Michael (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S299000, C438S585000, C438S592000

Reexamination Certificate

active

06284613

ABSTRACT:

BACKGROUND OF INVENTION
1) Field of the Invention
This invention relates generally to fabrication of gate electrodes for semiconductor devices and more particularly to the fabrication of a T-shaped gate electrode for an MOS semiconductor device.
2) Description of the Prior Art
As devices are made smaller, a major problem with semiconductor manufacturing is the forming of smaller gate length or widths while maintaining gate performance and forming proper low resistance silicide contacts. The gate must be narrow at the substrate to reduce the channel length but must be wide enough so that proper salicide contacts can be formed to the top of the gate. This is particularly important as gate width (or lenghts decrease below 0.25 &mgr;m). In order to increase the operation frequency of a device, it is in general required to shorten a length of a gate. However, further shortening of the gate length which is about 1 &mgr;m causes gate resistance to increase due to a smaller aspect ratio. Therefore, in order to prevent increase of the gate resistance while shortening the gate length further, a method in which a section of the gate is formed to have a T form is mostly used.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following patents.
U.S. Pat. No. 5,543,253(Park et al.) shows a T-gate process using one mask.
U.S. Pat. No. 5,688,704(Liu) shows a T-gate using 2 dielectric layers.
U.S. Pat. No. 5,861,327(Maeng et al.) teaches a T-gate using electroplating.
U.S. Pat. No. 5,658,826(Chung), U.S. Pat. No. 5,496,779(Lee et al.) and U.S. Pat. No. 5,498,560(Sharma et al.) show T-gates using other processes.
However, an improved process is need for a T-gate electrode.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for fabricating a t-shaped gate electrode.
It is an object of the present invention to provide a method for fabricating a t-shaped gate electrode that allows proper salicidation on the Top of the gate and allows gate bottom dimensions below 0.25 &mgr;m.
To accomplish the above objectives, the present invention provides a method of manufacturing a T-shaped gate electrode which is characterized as follows. A dummy gate composed of an insulating material is formed over the substrate. Then we form LDD regions adjacent to the dummy gate preferably by ion implanting (I/I) impurity ions into the substrate using the dummy gate as a mask. A pad oxide layer and dielectric layer are formed over the substrate surface. The dielectric layer over the dummy gate is removed preferably by a CMP process. We then remove the dummy gate to form a gate opening exposing the substrate surface. A gate dielectric layer is formed over the substrate surface in the gate opening. We form a polysilicon layer over the dielectric layer and the substrate surface in the gate opening. The polysilicon layer is patterned to form a T-gate. The dielectric layer is removed leaving the T-gate over the substrate. We forming source/drain (S/D) regions adjacent to the T-gate by an Ion implant process. A silicide layer is formed over the T-gate and the substrate to form silicide contacts to the S/D regions and gate contacts to the T-gate. We form a dielectric layer (ILD) over the T-gate and substrate. We form contact opening through the dielectric layer to expose the S/D regions and T-gate. We form contacts to the S/D regions and to the T-gate.
It is a major advantage of the invention's T-gate that the top gate
40
T is wide to allow the silicide to form property. If a conventional straight gate was used, the top of the gate would be too narrow to properly allow the silicide to form properly. The invention's T-gate allows the gate bottom
40
B to be made narrow (>0.25 &mgr;m) while the gate top
40
T is wider (e.g., >0.25) to allow a good silicide contact to allow a denser faster circuit. The invention avoids the poly gate line widening at the end of the gate contact.
Additional objects and advantages of the invention will be set forth in the description that follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of instrumentalities and combinations particularly pointed out in the append claims.


REFERENCES:
patent: 5496779 (1996-03-01), Lee et al.
patent: 5498560 (1996-03-01), Sharma et al.
patent: 5543253 (1996-08-01), Park et al.
patent: 5658826 (1997-08-01), Chung
patent: 5688704 (1997-11-01), Liu
patent: 5858843 (1999-01-01), Doyle et al.
patent: 5861327 (1999-01-01), Maeng et al.
patent: 5891783 (1999-04-01), Lin et al.
patent: 5937299 (1999-08-01), Michael et al.
patent: 5998285 (1999-12-01), Chou
patent: 6087248 (2000-07-01), Rodder
patent: 6117741 (2000-09-01), Chatterjee et al.
patent: 8-162634 (1996-06-01), None

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